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參數(shù)資料
| 型號： | MPE603ERX100LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | CERAMIC, BGA-255 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大小： | 135K |
| 代理商： | MPE603ERX100LX |
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2
EC603e Microprocessor Hardware Specifications (PID6)
To locate any published errata or updates for this document, refer to the website at http://www.mot.com/
SPS/PowerPC/.
1.1 Overview
The PID6 implementation of the EC603e microprocessor is a low-power implementation of the PowerPC
microprocessor family of reduced instruction set computer (RISC) microprocessors. The PID6 implements
the 32-bit portion of the PowerPC architecture specication, which provides 32-bit effective addresses, and
integer data types of 8, 16, and 32 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture
provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit
architecture.
The PID6 provides four software controllable power-saving modes. Three of the modes (the nap, doze, and
sleep modes) are static in nature, and progressively reduce the amount of power consumed by the processor.
The fourth is a dynamic power management mode that causes the functional units in the PID6 to
automatically enter a low-power mode when the functional units are idle without affecting operational
performance, software execution, or any external hardware.
The PID6 is a superscalar processor capable of issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased performance; however, the PID6 makes completion
appear sequential.
The PID6 integrates four execution units—an integer unit (IU), a branch processing unit (BPU), a load/store
unit (LSU), and a system register unit (SRU). The ability to execute ve instructions in parallel and the use
of simple instructions with rapid execution times yield high efciency and throughput for PID6–based
systems. Most integer instructions execute in one clock cycle.
The PID6 provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches
for instructions and data, as well as on-chip instruction and data memory management units (MMUs). The
MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB
and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized
block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The PID6
also supports block address translation through the use of two independent instruction and data block
address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared
simultaneously with all four entries in the BAT array during block translation. In accordance with the
PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes
priority.
The PID6 has a selectable 32- or 64-bit data bus and a 32-bit address bus. The PID6 interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The PID6 provides a
three-state coherency protocol that supports the exclusive, modied, and invalid cache states. This protocol
is a compatible subset of the MESI (modied/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The PID6 supports single-beat and burst data transfers
for memory accesses, and supports memory-mapped I/O.
The PID6 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility
with TTL devices.
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