參數(shù)資料
型號(hào)： MPC8240EC
廠商： Motorola, Inc.
英文描述： Integrated Processor Hardware Specifications
中文描述： 綜合處理器硬件規(guī)格
文件頁(yè)數(shù)： 4/52頁(yè)
文件大小： 1027K
代理商： MPC8240EC
4
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Features
– Address translation unit
– Some internal configuration registers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/Port X not supported)
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering—Read or write discontinuous memory
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– PCI-to-local memory
– PCI memory-to-local memory
— Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I
2
O message controller
— I
2
C controller with full master/slave support (except broadcast all)
— Programmable interrupt controller (PIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers
— Integrated PCI bus, CPU, and SDRAM clock generation
— Programmable PCI bus, 60x, and memory interface output drivers
Dynamic power management—Supports 60x nap, doze, and sleep modes
Programmable input and output signals with watchpoint capability
Built-in PCI bus performance monitor facility
— Debug features
– Memory attribute and PCI attribute signals
– Debug address signals
– MIV signal—Marks valid address and data bus cycles on the memory bus
– Error injection/capture on data path
– IEEE 1149.1 (JTAG)/test interface
Processor core interface
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and a branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 cache, entire cache or on a per-way basis
F
Freescale Semiconductor, Inc.
n
.
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