參數(shù)資料
型號： MPC8240EC
廠商： Motorola, Inc.
英文描述： Integrated Processor Hardware Specifications
中文描述： 綜合處理器硬件規(guī)格
文件頁數(shù)： 34/52頁
文件大?。?/td> 1027K
代理商： MPC8240EC
34
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
PLL Configurations
1.6
PLL Configurations
The MPC8240 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN
(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)
frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO)
frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the
MPC8240 is shown in Table 18.
Table 18. MPC8240 Microprocessor PLL Configurations
Ref.
No.
PLL_CFG
[0:4]
2
CPU
1
HID1
[0:4]
200 MHz Part
8,9
Ratios
3,4
PCI Clock Input
(PCI_SYNC_IN)
Range (MHz)
Peripheral
Logic/ Mem Bus
Clock Range
(MHz)
CPU Clock
Range
(MHz)
PCI-to-Mem
(Mem VCO)
Multiplier
Mem-to-CPU
(CPU VCO)
Multiplier
0
00000
00110
25–26
75–80
188–200
3 (6)
2.5 (5)
1
00001
11000
Not usable
3 (6)
3 (6)
2
00010
00101
50–56
5
50 – 56
100–112
1 (4)
2 (8)
3
00011
00101
Bypass
Bypass
2 (8)
4
00100
00101
25–28
5
50–56
100–113
2 (8)
2 (8)
5
00101
00110
Bypass
Bypass
2.5 (5)
7
00111
11000
Bypass
Bypass
3 (6)
8
01000
11000
33
6
–56
5
33–56
100–168
1 (4)
3 (6)
A
01010
00111
Not usable
2 (4)
4.5 (9)
C
01100
00110
25–40
50–80
125–200
2 (4)
2.5 (5)
E
01110
11000
25–33
50–66
150–200
2 (4)
3 (6)
10
10000
00100
25–33
33
7
–66
75–100
150–200
3 (6)
2 (4)
12
10010
00100
50–100
100–200
1.5 (3)
2 (4)
14
10100
11110
25–28
50–56
175–200
2 (4)
3.5 (7)
16
10110
11010
25
50
200
2 (4)
4 (8)
18
11000
11000
25–26
62–65
186–200
2.5 (5)
3 (6)
1A
11010
11010
50
50
200
1 (2)
4 (8)
1C
11100
11000
33
7
–44
33
7
–53
50–66
150–200
1.5 (3)
3 (6)
1D
11101
00110
50–80
125–200
1.5 (3)
2.5 (5)
F
Freescale Semiconductor, Inc.
n
.
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