參數(shù)資料
型號(hào)： MPC8240EC
廠商： Motorola, Inc.
英文描述： Integrated Processor Hardware Specifications
中文描述： 綜合處理器硬件規(guī)格
文件頁(yè)數(shù)： 13/52頁(yè)
文件大小： 1027K
代理商： MPC8240EC
MOTOROLA
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
13
Electrical and Thermal Characteristics
Figure 6 shows the PCI_SYNC_IN input clock timing diagram, and Figure 7 shows the DLL locking range
loop delay versus frequency of operation.
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
16
DLL lock range with DLL_STANDARD = 0 (default)
0
≤
(NT
clk
– T
clk
/2 – t
loop
– t
fix0
)
7
ns
7
17
Frequency of operation (OSC_IN)
25
66
MHz
18
OSC_IN cycle time
40
15
ns
19
OSC_IN rise and fall times
—
5
ns
5
20
OSC_IN duty cycle measured at 1.4 V
40
60
%
21
OSC_IN frequency stability
—
100
ppm
22
OSC_IN V
IH
(loaded)
2.0
V
23
OSC_IN V
IL
(loaded)
0.8
V
Notes
:
1. These specifications are for the default driver strengths indicated in Table 4.
2. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
3. Specification value at maximum frequency of operation.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Rise and fall times for the OSC_IN input are guaranteed by design and characterization. OSC_IN input rise and fall
times are not tested.
6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after
a stable V
DD
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
7. DLL_STANDARD is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). T
clk
is the period of one
SDRAM_SYNC_OUT clock cycle in ns. t
loop
is the propagation delay of the DLL synchronization feedback loop (PC
board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC
board runner) corresponds to approximately 1 ns of delay. t
fix0
is a fixed delay inherent in the design when the DLL
is at tap point 0 and the DLL is contributing no delay; t
fix0
equals approximately 3 ns. See Figure 7 for DLL3 locking
ranges.
8. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any
intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is,
the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is
locked. While pin to pin skew between SDRAM_CLKs can be measured, the relationship between the internal
sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design.
Table 7. Clock AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with LV
DD
= 3.3 V ± 0.3 V
Num
Characteristic and Condition
1
Min
Max
Unit
Notes
5a
5b
VM
VM = Midpoint Voltage (1.4 V)
2
3
CV
IL
CV
IH
1
PCI_SYNC_IN
VM
VM
F
Freescale Semiconductor, Inc.
n
.
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