參數(shù)資料
型號: MC68MH360ZQ25LR2
廠商: Freescale Semiconductor
文件頁數(shù): 80/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 25MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
QMC Supplement
Figure 1-8. Frame Structures for E1/CEPT and T1 TDM Interfaces
For any station to receive and transmit on a TDM line, it is necessary for it to determine the
correct time slot boundary. The service provider or the PTT provides a 4-wire interface with
a continuous bit stream coming down the line. The T1 and E1 have information embedded
in the data stream that delineates frames. The bit pattern in position 193 in T1 over a period
of several frames establishes a synchronization pattern. A station may have the capability
to search for this pattern and thus nd the correct time for frame synchronization. In a
similar way, time slots 0 and 16 are reserved not only for synchronization but also for
signaling in the E1 interface.
Depending on its capability, a node can either extract this synchronization information or
it can be supported by framer and time slot assigner devices.
Framing Bit 193
FRAME STRUCTURE FOR T1 1.544 MBPS
193 BITS/125
S
0
1
22
23
0
256 Bits/125
s
Framing (TS0)
Frame Structure for E1 2.048 Mbps
Signaling (TS16)
12
31
30
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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