參數(shù)資料
型號: MC68MH360ZQ25LR2
廠商: Freescale Semiconductor
文件頁數(shù): 54/158頁
文件大小: 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 25MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
Appendix C. Connecting ISDN Multiple S/T or U Interfaces to QUICC32
C.3.1.2 Deactivation Procedure
When the clock-master S/T interface is deactivated, the QUICC32 receives an interrupt
indicating the deactivation status (IRQ3 —register NR3 bit 3— meaning Info 0 of
Figure C-9 has been received). Then, if another S/T interface is active, its TCLK signal
must be selected to become the clock master; otherwise, the QUICC32 can select the BRG
to be the clock master.
As shown in Figure C-9, the TCLK signal is disabled about 72.8
s after the interruption.
Therefore, the QUICC32 has 72.8
s to react to the IRQ and to select another clock master.
Figure C-9. Timing Diagram for a Deactivation (Always Initiated by the NT)
Info 3
TX
RX
TX
RX
Info 4
RX
TX
Info 0
TCLK
IRQ3
TE
NT
1
2
1: 500 ms (= 2 S/T Frames x 250 ms)
2: 72.8 ms (= 14 bit x 5.2 ms)
Info 0
TX
RX
IRQ3
Disabled
(Rx Info 0)
Time
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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