參數(shù)資料
型號： MC68MH360ZQ25LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 39/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Appendix B. Frequently-Asked Questions
A hybrid approach runs a single line of up to 64 multiplexed time slots to two
separate SCCs, each with its own set of parameters. Normally this would route
32 time slots to each SCC. This would have the benet of doubling your effective
FIFO depth, allowing greater system design exibility.
Q: My understanding is that the MH360 could not support the SS-7 microcode. Is this
also true of the 860MH?
A: The 860MH will not support SS-7 over the multiplexed (QMC) channels. If SS-7 is
to be run, it must be run over its own dedicated SCC. However, by using the time
slot assigner, the trafc from this SCC could be routed over the same E1 or T1 as the
other multiplexed HDLC channels.
For example, one channel of an E1 could be routed to an SCC running SS-7, and the
other 31 channels to an SCC running QMC. Thus, the number of SS-7 channels
allowed is limited to the number of SCCs (that is, at most 4).
Q: What is the CPM’s maximum CPU bus utilization when running two 2-Mbps QMC
channels?
A: For 64 channels (two E1 lines), two 2-Mbps full duplex means 8 Mbps of aggregate
trafc. Factoring in a large margin for buffer descriptor accesses bumps this 8 Mbps
up to 10 Mbps. The 10 Mbps of trafc translates to 0.3 megatransfers of 32 bits each
requiring only 1.5 MHz out of a 50-MHz bus (assuming a 5 wait-state memory). A
similar calculation for Ethernet would account for higher data trafc and fewer
descriptor accesses.
Q: Is the 860MH pin compatible with the 860DH?
A: Yes, it is pin compatible.
Q: Are BISYNC and Centronics still removed from the 860MH as they are with the
MH360?
A: No, Centronics and Bisync are both supported on the 860MH.
Q: How is time slot 0 identied on an SCC? Is an external sync required?
A: The TSA identies time slot 0. A sync pulse must be provided to the TSA at the
beginning of a frame.
Q: What does the larger dual-ported RAM on the 860MH provide?
A: The larger dual-ported RAM means that up to 64 QMC channels may be supported.
It also provides more buffer descriptor area needed for the higher serial performance
at higher speeds.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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