參數(shù)資料
型號： MC68MH360ZQ25LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 21/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Chapter 9. Multi-Subchannel (MSC) Microcode
Chapter 9
Multi-Subchannel (MSC) Microcode
90
The RISC processor in the PowerQUICC has an option to execute microcode from the
internal dual-ported RAM. Motorola uses this feature to enhance existing protocols or
implement additional protocols. Customers can purchase RAM microcodes in an object-
code format and download it to the PowerQUICC dual-ported RAM during system
initialization.
The RAM microcode is provided by Motorola as a set of S records that can be downloaded
directly to an application development system or stored in a system EPROM; for more
information on S records, see Appendix C of the M68000 Family Programmer’s Reference
Manual. After system reset, the binary of the microcode should be copied to the dual-ported
RAM. The QUICC registers, including the RISC controller conguration register (RCCR),
should be initialized as specied in the microcode RAM documentation. Before the RISC
is used in the system, the user should issue a reset command to the communications
processor command register (CR). The microcode RAM functions are available in addition
to all protocols available in the standard QUICC microcode ROM.
9.1 MSC Microcode Features
The multi-subchannel (MSC) microcode is a downloadable microcode for the MPC860MH
and has the following key features:
General
— Multiple subchannels within a single 8-bit time slot
— Bit resolution for subchannels
— Up to 32 independent communications channels for both Rx and Tx
— Supports either transparent or HDLC protocols per subchannel
Performance
— 32 channels + 10-Mbps ethernet support at 40-MHz system clock
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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