參數(shù)資料
型號: MC68MH360ZQ25LR2
廠商: Freescale Semiconductor
文件頁數(shù): 115/158頁
文件大小: 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
標準包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 25MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應商設備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
QMC Supplement
CONTENTS
Paragraph
Number
Title
Page
Number
2.1.9
Data Buffer .......................................................................................................2-5
2.2
Global Multichannel Parameters ..........................................................................2-5
2.3
Multiple SCC Assignment Tables ......................................................................2-10
2.4
Channel-Specific Parameters..............................................................................2-14
2.4.1
Channel-Specific HDLC Parameters..............................................................2-14
2.4.1.1
CHAMR—Channel Mode Register (HDLC).............................................2-15
2.4.1.2
TSTATE—Tx Internal State (HDLC)........................................................2-17
2.4.1.3
INTMSK—Interrupt Mask (HDLC) ..........................................................2-18
2.4.1.4
RSTATE—Rx Internal State (HDLC) .......................................................2-19
2.4.2
Channel-Specific Transparent Parameters .....................................................2-20
2.4.2.1
CHAMR—Channel Mode Register (Transparent Mode) ..........................2-21
2.4.2.2
TSTATE—Tx Internal State (Transparent Mode) .....................................2-23
2.4.2.3
INTMSK—Interrupt Mask (Transparent Mode)........................................2-24
2.4.2.4
TRNSYNC—Transparent Synchronization ...............................................2-24
2.4.2.5
RSTATE—Rx Internal State (Transparent Mode).....................................2-28
Chapter 3
QMC Commands
3.1
Transmit Commands.............................................................................................3-1
3.2
Receive Commands ..............................................................................................3-2
Chapter 4
QMC Exceptions
4.1
Global Error Events ..............................................................................................4-2
4.1.1
Global Underrun (GUN)...................................................................................4-3
4.1.2
Global Overrun (GOV) in the FIFO .................................................................4-3
4.1.3
Restart from a Global Error ..............................................................................4-3
4.2
SCC Event Register (SCCE) ................................................................................4-3
4.3
Interrupt Table Entry ............................................................................................4-5
4.4
Channel Interrupt Processing Flow ......................................................................4-7
Chapter 5
Buffer Descriptors
5.1
Receive Buffer Descriptor ....................................................................................5-1
5.2
Transmit Buffer Descriptor ..................................................................................5-5
5.3
Placement of Buffer Descriptors ..........................................................................5-7
5.3.1
MC68MH360 Internal Memory Structure........................................................5-7
5.3.2
Parameter RAM Usage for QMC over Several SCCs......................................5-9
5.3.3
MPC860MH Internal Memory Structure .......................................................5-14
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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