參數(shù)資料
型號： MC68MH360ZQ25LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 108/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Chapter 2. QMC Memory Organization
2.4.2.2 TSTATE—Tx Internal State (Transparent Mode)
TSTATE denes the internal transmitter state. The high byte of TSTATE denes the
function code/address type and the Motorola/Intel bit (bit 3) that should always be set to 1.
Figure 2-12 shows the TSTATE register for transparent mode.
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 2-12. TSTATE—Tx Internal State (Transparent Mode)
For the MH360, TSTATE should be host-initialized to 0x3800_0000 before enabling the
channel—function code 8. Table 2-12 describes the TSTATE elds for the MH360 with
boldfaced parameters to be initialized by the user.
For the 860MH, TSTATE should be host-initialized to 0x3000_0000 before enabling the
channel—AT = 0. Note that for the 860MH bit 4 should always be zero as only bits 5–7
map to AT[1–3]. Table 2-13 describes the TSTATE elds for the 860MH with boldfaced
parameters to be initialized by the user.
01234567
0
1
MOT
FC[3–0]/ AT[1–3]
Table 2-12. TSTATE Field Descriptions for MH360 (Transparent Mode)
Field
Name
Description
0–1
—
0
2—
1
3
MOT
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
4–7
FC[3–0]
Function code—This eld contains the function code for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Function codes are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
Table 2-13. TSTATE Field Descriptions for 860MH (Transparent Mode)
Field
Name
Description
0–1
—
0
2—
1
3
MOT
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
4—
0
5–7
AT[1–3]
Address type—This eld contains the address type for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Address types are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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