
MOTOROLA
iv
MC68HC11KW1
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TITLE
5.1.3
5.1.3.1
5.1.4
5.1.5
5.1.6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.2.11
5.2.12
5.3
5.3.1
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.5
5.5.1
5.5.2
COP reset........................................................................................................5-2
COPRST — Arm/reset COP timer circuitry register...................................5-3
Clock monitor reset..........................................................................................5-3
OPTION — System configuration options register 1 .......................................5-4
CONFIG — Configuration control register.......................................................5-5
Effects of reset.......................................................................................................5-6
Central processing unit....................................................................................5-7
Memory map....................................................................................................5-7
Parallel I/O.......................................................................................................5-7
Timer 1.............................................................................................................5-7
Timers 2 and 3.................................................................................................5-8
Real-time interrupt (RTI)..................................................................................5-8
Pulse accumulator ...........................................................................................5-8
Computer operating properly (COP)................................................................5-8
Serial communications interface (SCI).............................................................5-8
Serial peripheral interface (SPI).......................................................................5-9
Analog-to-digital converter...............................................................................5-9
System.............................................................................................................5-9
Reset and interrupt priority....................................................................................5-9
HPRIO — Highest priority I-bit interrupt and misc. register .............................5-10
Interrupts ...............................................................................................................5-13
Interrupt recognition and register stacking.......................................................5-13
Nonmaskable interrupt request (XIRQ) ...........................................................5-14
Illegal opcode trap ...........................................................................................5-14
Software interrupt ............................................................................................5-14
Maskable interrupts .........................................................................................5-15
Reset and interrupt processing........................................................................5-15
Low power operation .............................................................................................5-15
WAIT................................................................................................................5-15
STOP...............................................................................................................5-16
6
PARALLEL INPUT/OUTPUT
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.4
6.4.1
Port A.....................................................................................................................6-2
PORTA — Port A data register ........................................................................6-2
DDRA — Data direction register for port A......................................................6-2
Port B.....................................................................................................................6-3
PORTB — Port B data register........................................................................6-3
DDRB — Data direction register for port B......................................................6-3
Port C ....................................................................................................................6-4
PORTC — Port C data register........................................................................6-4
DDRC — Data direction register for port C......................................................6-4
Port D ....................................................................................................................6-5
PORTD — Port D data register........................................................................6-5
TPG
6