
MOTOROLA
3-14
MC68HC11KW1
CENTRAL PROCESSING UNIT
3
SUBA (opr)
Subtract memory fromA
A – M
 A
A
A
A
A
A
IMM
DIR
EXT
IND, X
IND, Y
80
90
B0
A0
18 A0
ii
dd
hh ll
ff
ff
2
3
4
4
5
— — — —
 
SUBB (opr)
Subtract memory fromB
B – M
 B
B
B
B
B
B
IMM
DIR
EXT
IND, X
IND, Y
C0
D0
F0
E0
18 E0
ii
dd
hh ll
ff
ff
2
3
4
4
5
— — — —
 
SUBD (opr)
Subtract memory fromD
D – M:M+1 
 D
IMM
DIR
EXT
IND, X
IND, Y
83
93
B3
A3
18 A3
jj
dd
hh ll
ff
ff
kk
4
5
6
6
7
— — — —
 
SWI
Software interrupt
see Figure 3-2
A 
 B
A 
 CCR
B 
 A
address bus increments
CCR 
 A
M– 0
INH
3F
—
14
— — — 1 — — — —
— — — —
 
 ↓
— — — —
 
— — — — — — — —
TAB
Transfer A to B
INH
16
—
2
0 —
0 —
TAP
Transfer A to CC register
INH
06
—
2
TBA
Transfer B to A
INH
17
—
2
TEST
Test (only in test modes)
INH
00
—
TPA
Transfer CC register to A
INH
07
—
2
— — — — — — — —
— — — —
 
TST (opr)
Test for zero or mnus
EXT
IND, X
IND, Y
7D
6D
18 6D
hh ll
ff
ff
6
6
7
0 0
TSTA
Test A for zero or mnus
A – 0
A
INH
4D
—
2
— — — —
 
— — — —
 
— — — — — — — —
0 0
TSTB
Test B for zero or mnus
B – 0
B
INH
5D
—
2
0 0
TSX
Transfer stack pointer to X
SP + 1 
 IX
SP + 1 
 IY
IX – 1 
 SP
IY – 1 
 SP
stack registers & WAIT
IX 
 D; D 
 IX
IY 
 D; D 
 IY
INH
30
—
3
TSY
Transfer stack pointer to Y
INH
18 30
—
4
— — — — — — — —
TXS
Transfer X to stack pointer
INH
35
—
3
— — — — — — — —
TYS
Transfer Y to stack pointer
INH
18 35
—
4
— — — — — — — —
WAI
Wait for interrupt
INH
3E
—
— — — — — — — —
XGDX
Exchange D with X
INH
8F
—
3
— — — — — — — —
XGDY
Exchange D with Y
INH
18 8F
—
4
— — — — — — — —
Operators
Operands
Is transferred to
Boolean AND
Arithmetic addition, except where used as an
     inclusive-OR symbol in Boolean formulae
Exclusive-OR
Multiply
Concatenation
Arithmetic subtraction, or negation symbol
     (Twos complement)
dd
8-bit direct address ($0000–$00FF); the high byte is assumed
      to be zero
8-bit positive offset ($00 to $FF (0 to 256)) is added to the
      contents of the index register
High order byte of 16-bit extended address
One byte of immediate data
High order byte of 16-bit immediate data
Low order byte of 16-bit immediate data
Low order byte of 16-bit extended address
8-bit mask (set bits to be affected)
Signed relative offset ($80 to $7F (–128 to +127));
      offset is relative to the address following the offset byte
+
ff
⊕
hh
*
:
–
ii
jj
kk
ll
mm
rr
Cycles
Condition Codes
—
0
1
↓
Infinite, or until reset occurs
12 cycles are used, beginning with the opcode
     fetch. A wait state is entered, which remains
     in effect for an integer number of MPU E clock
     cycles (n) until an interrupt is recognised.
     Finally, two additional cycles are used to fetch
     the appropriate interrupt vector. (14 + n, total).
Bit not changed
Bit always cleared
Bit always set
Bit set or cleared, depending on the operation
Bit can be cleared, but cannot become set
Not defined
Table 3-2   
Instruction set  (Page 6 of 6)
Mnemonic
Operation
Description
Addressing
mode
Instruction
Condition codes
Opcode
Operand
Cycles
S X H
I N Z V C
TPG
42