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MC68HC11KW1
MOTOROLA
xi
LIST OF FIGURES
Figure
Number
Page
Number
TITLE
LIST OF FIGURES
1-1
2-1
2-2
2-3
2-4
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
5-1
5-2
5-3
5-4
5-5
5-6
7-1
7-2
7-3
8-1
8-2
9-1
9-2
9-3
9-4
9-5
9-6
9-7
A-1
A-2
MC68HC11KW1 block diagram..............................................................................1-3
MC68HC11KW1 100-pin TQFP..............................................................................2-1
External reset circuitry............................................................................................2-2
Oscillator connections ............................................................................................2-3
RAM stand-by connections.....................................................................................2-5
Programming model ...............................................................................................3-1
Stacking operations................................................................................................3-3
MC68HC11KW1 memory map...............................................................................4-3
RAM and register overlap.......................................................................................4-14
Memory map example of memory expansion.........................................................4-25
Schematic example of memory expansion.............................................................4-26
Memory map example of memory expansion.........................................................4-27
Schematic example of memory expansion.............................................................4-28
Processing flow out of reset (1 of 2).......................................................................5-17
Processing flow out of reset (2 of 2).......................................................................5-18
Interrupt priority resolution (1 of 3).........................................................................5-19
Interrupt priority resolution (2 of 3).........................................................................5-20
Interrupt priority resolution (3 of 3).........................................................................5-21
Interrupt source resolution within the SCI subsystem ............................................5-22
SCI baud rate generator circuit diagram.................................................................7-1
SCI block diagram ..................................................................................................7-3
Interrupt source resolution within SCI.....................................................................7-14
SPI block diagram...................................................................................................8-2
SPI transfer format..................................................................................................8-3
Timer clock divider chains ......................................................................................9-2
Timer 1 capture/compare block diagram................................................................9-5
Timer 2 capture/compare block diagram................................................................9-17
Timer 3 capture/compare block diagram................................................................9-25
Pulse accumulator block diagram...........................................................................9-34
PWM timer block diagram.......................................................................................9-39
PWM duty cycle......................................................................................................9-44
Test methods......................................................................................................... A-3
Timer inputs........................................................................................................... A-5
TPG
11