
MOTOROLA
4-6
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
4
Timer interrupt flag 1 (TFLG1)
$0023
OC1F
OC2F
OC3F
OC4F I4/O5F
IC1F
IC2F
IC3F
0000 0000
Timer interrupt mask 2 (TMSK2)
$0024
TOI
RTII
PAOVI
PAII
0
0
PR1
PR0
0000 0000
Timer interrupt flag 2 (TFLG2)
$0025
TOF
RTIF PAOVF
PAIF
0
0
0
0
0000 0000
Pulse accumulator control (PACTL)
$0026
0
PAEN PAMODPEDGE
0
I4/O5
RTR1 RTR0 0000 0000
Pulse accumulator count (PACNT)
$0027
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
SPI control (SPCR)
$0028
SPIE
SPE
DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu
SPI status (SPSR)
$0029
SPIF
WCOL
0
MODF
0
0
0
0
0000 0000
SPI data (SPDR)
$002A
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Reserved
$002B
Port pull-up assignment (PPAR)
$002C
0
0
0
0
HPPUEGPPUE FPPUE BPPUE 0000 1111
Port G assignment (PGAR)
$002D
0
0
PGAR5PGAR4PGAR3PGAR2PGAR1PGAR0 0000 0000
Reserved
$002E
Reserved
$002F
A/D control & status (ADCTL)
$0030
CCF CONV8 SCAN MULT
CD
CC
CB
CA
0000 0000
Compare force for timers 2 and 3 (F23FRC)
$0031 FT3C1 FT3C2 FT3C3 FT3C4 FT2C1 FT2C2 FT2C3 FT2C4 0000 0000
A/D frequency select (ADFRQ)
$0032
0
0
0
0
0
0
0
ADER 0000 0000
Reserved
$0033
Reserved
$0034
Block protect (BPROT)
$0035 BULKP BIT6 BPRT4PTCONBPRT3 BPRT2 BPRT1 BPRT0 1111 1111
Reserved
$0036
EEPROM mapping (INIT2)
$0037
EE3
EE2
EE1
EE0
0
0
0
0
0000 0000
Systemconfig. options 2 (OPT2)
$0038
LIRDV CWOM
0
IRVNE LSBF
SPR2 XDV1 XDV0 000x 0000
Systemconfig. options 1 (OPTION)
$0039
ADPU CSEL
IRQE
DLY
CME
FCME
CR1
CR0
0001 0000
COP timer arm/reset (COPRST)
$003A
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
EEPROM programmng (PPROG)
$003B
ODD
EVEN
0
BYTE
ROW ERASE EELATEM
0000 0000
Highest priority interrupt (HPRIO)
$003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
RAM& I/O mapping (INIT)
$003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000
Factory test (TEST1)
$003E
TILOP
0
OCCR CBYP
DISR
FCM FCOP
0
0000 x000
Configuration control (CONFIG)
$003F
1
1
CLKX PARENNOSECNP
1
EEON 11xx xx1x
A/D result 1 (ADR1) high
$0040
(Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 1 (ADR1) low
$0041
(7)
(6)
0
0
0
0
0
0
uu00 0000
A/D result 2 (ADR2) high
$0042
(Bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
undefined
A/D result 2 (ADR2) low
$0043
(7)
(6)
0
0
0
0
0
0
uu00 0000
Table 4-2
Register and control bit assignments (Page 2 of 5)
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
TPG
48