
MOTOROLA
4-8
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
4
Pulse width count 2 (PWCNT2)
$0065
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width count 3 (PWCNT3)
$0066
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width count 4 (PWCNT4)
$0067
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width period 1 (PWPER1)
$0068
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width period 2 (PWPER2)
$0069
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width period 3 (PWPER3)
$006A
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width period 4 (PWPER4)
$006B
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width duty 1 (PWDTY1)
$006C
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width duty 2 (PWDTY2)
$006D
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width duty 3 (PWDTY3)
$006E
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width duty 4 (PWDTY4)
$006F
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
SCI baud rate high (SCBDH)
$0070
BTST
BSPL SYNC SBR12 SBR11 SBR10 SBR9 SBR8 0000 0000
SCI baud rate low (SCBDL)
$0071
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0000 0100
SCI control 1 (SCCR1)
$0072 LOOPS WOMS
0
M
WAKE
ILT
PE
PT
0000 0000
SCI control 2 (SCCR2)
$0073
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0000 0000
SCI status 1 (SCSR1)
$0074
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1100 0000
SCI status 2 (SCSR2)
$0075
0
0
0
0
0
0
0
RAF
0000 0000
SCI data high (SCDRH)
$0076
R8
T8
0
0
0
0
0
0
undefined
SCI data low (SCDRL)
$0077
R7T7
R6T6
R5T5
R4T4
R3T3
R2T2
R1T1
R0T0
undefined
Reserved
$0078
Reserved
$0079
Reserved
$007A
Reserved
$007B
Port H data (PORTH)
$007C
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
undefined
Data direction H (DDRH)
$007D
DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 0000 0000
Port G data (PORTG)
$007E
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
undefined
Data direction G (DDRG)
$007F
0
0
DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000
Timer control register 3 (TCTL3)
$0080
OM1
OL1
OM2
OL2
OM3
OL3
OM4
OL4
0000 0000
Timer control register 4 (TCTL4)
$0081
EDGB EDGA PR2B PR2A ECEB ECEA T2STP
I1/04
0000 0000
Timer 2 counter register (TCNT2) high $0082
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 0000 0000
Timer 2 counter register (TCNT2) low $0083
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Timer 2 output compare 1(T2OC1)
high
$0084
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer 2 output compare 1 (T2OC1) low $0085
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer 2 output comp. 2 (T2OC2) high $0086
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Table 4-2
Register and control bit assignments (Page 4 of 5)
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
TPG
50