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MOTOROLA
ii
MC68HC11KW1
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TITLE
3
CENTRAL PROCESSING UNIT
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.6.1
3.1.6.2
3.1.6.3
3.1.6.4
3.1.6.5
3.1.6.6
3.1.6.7
3.1.6.8
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
Registers ...............................................................................................................3-1
Accumulators A, B and D.................................................................................3-2
Index register X (IX).........................................................................................3-2
Index register Y (IY) .........................................................................................3-2
Stack pointer (SP)............................................................................................3-2
Program counter (PC)......................................................................................3-4
Condition code register (CCR).........................................................................3-4
Carry/borrow (C) ........................................................................................3-5
Overflow (V) ...............................................................................................3-5
Zero (Z)......................................................................................................3-5
Negative (N)...............................................................................................3-5
Interrupt mask (I)........................................................................................3-5
Half carry (H)..............................................................................................3-6
X interrupt mask (X)...................................................................................3-6
Stop disable (S)..........................................................................................3-6
Data types .............................................................................................................3-6
Opcodes and operands.........................................................................................3-7
Addressing modes.................................................................................................3-7
Immediate (IMM) ...................................................................................................3-7
Direct (DIR)......................................................................................................3-7
Extended (EXT) ...............................................................................................3-8
Indexed (IND, X; IND, Y)...................................................................................3-8
Inherent (INH)..................................................................................................3-8
Relative (REL)..................................................................................................3-8
Instruction set........................................................................................................3-8
4
OPERATING MODES AND ON-CHIP MEMORY
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.3
4.3.1
4.3.1.1
Operating modes...................................................................................................4-1
Single chip operating mode .............................................................................4-1
Expanded operating mode...............................................................................4-1
Special test mode ............................................................................................4-2
Special bootstrap mode...................................................................................4-2
On-chip memory....................................................................................................4-3
Mapping allocations.........................................................................................4-3
RAM...........................................................................................................4-4
Bootloader ROM ........................................................................................4-4
Registers..........................................................................................................4-4
System initialization...............................................................................................4-10
Mode selection.................................................................................................4-10
HPRIO — Highest priority I-bit interrupt & misc. register ...........................4-11
TPG
4