
APPE NDIX
Appendix 2. Memory assignment in SFR area
7721 Group User’s Manual
17–6
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
60
16
61
16
62
16
63
16
64
16
65
16
66
16
67
16
68
16
69
16
6A
16
70
16
71
16
72
16
73
16
74
16
75
16
76
16
77
16
78
16
79
16
7A
16
7B
16
7C
16
7D
16
7E
16
7F
16
6B
16
6C
16
6D
16
6E
16
6F
16
Address
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
INT
2
interrupt control register
Watchdog timer frequency select register
Real-time output control register
Register name
Watchdog timer register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
INT
1
interrupt control register
Access characteristics
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
b7
b0
RW
RW
RW
State immediately after reset
b7
0
0
(Note 6)
0
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
By writing dummy data to address 60
16
, the value “FFF
16
” is set to the watchdog timer.
The dummy data is not retained anywhere.
The value “FFF
16
” is set to the watchdog timer. (Refer to “
CHAPTER
15. WATCHDOG TIMER
.”)
It is possible to read the bit state at reading. When writing “0” to this bit, this bit becomes “0.”
But when writing “1” to this bit, this bit does not change.
RW
Notes 5:
6:
7:
(Note 5)
RW
0
0
0
0
0
0
0
0
0
0
Refresh timer
DMAC control
register
L
DMAC control
register
H
DMA0 interrupt control register
DMA1 interrupt control register
DMA2 interrupt control register
DMA3 interrupt control register
RW
0
0
0
0
0
0
RW
RW
DRAM control
register
WO
RW
(Note 7)
RW
WO
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 : “0” immediately after reset.
1 : “1” immediately after reset.
:
Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
0
1
0
0
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
State immediately after reset