
T IME R A
7721 Group User’s Manual
8–24
8.4 Event counter mode
8.4.3 Switching between countup and countdown
The up-down register (address 44
16
) or the input signal from the TAj
OUT
pin is used to switch countup from
and to countdown. This switching is performed by the up-down bit when the up-down switching factor select
bit (bit 4 at addresses 58
16
to 5A
16
) is “0,” and by the input signal from the TAj
OUT
pin when the up-down
switching factor select bit is “1.”
When the switching between countup and countdown is set while counting is in progress, this switching is
actually performed when the count source’s next valid edge is input.
(1)
Switching by up-down bit
Countdown is performed when the up-down bit is “0,” and countup is performed when the up-down
bit is “1.” Figure 8.4.5 shows the structure of the up-down register.
(2)
Switching by TAj
OUT
pin’s input signal
Countdown is performed when the TAj
OUT
pin’s input signal is at “L” level, and countup is performed
when the TAj
OUT
pin’s input signal is at “H” level.
When using the TAj
OUT
pin’s input signal to switch countup from and to countdown, set the port P5
direction register’s bit which corresponds to the TAj
OUT
pin for the input mode.
Fig. 8.4.5 Structure of up-down register
Bit
Bit name
At reset
0
0
0
0
0
RW
Functions
b7
b6
b5
b4
b3
b2
b1
b0
Up-down register (Address 44
16
)
0
0
0
Timer A4 up-down bit
Timer A3 up-down bit
Timer A2 up-down bit
Fix these bits to “0.”
Timer A2 two-phase pulse signal
processing select bit
(Note)
Timer A3 two-phase pulse signal
processing select bit
(Note)
Timer A4 two-phase pulse signal
processing select bit
(Note)
0 : Countdown
1 : Countup
This function is valid when the contents of
the up-down register is selected as the up-
down switching factor.
0 : Two-phase pulse signal
processing function disabled
1 : Two-phase pulse signal
processing function enabled
When not using the two-phase pulse
signal processing function, set the bit
to “0.”
The value is “0” at reading.
Note:
Use the
LDM
or
STA
instruction for writing to bits 5 to 7.
0
1
2
3
4
5
6
7
RW
RW
RW
RW
RW
WO
WO
WO
0 0