
APPE NDIX
7721 Group User’s Manual
17–5
Appendix 2. Memory assignment in SFR area
RW
RW
RW
Timer B2 register
40
16
41
16
42
16
43
16
44
16
45
16
46
16
47
16
48
16
49
16
4A
16
50
16
51
16
52
16
53
16
54
16
55
16
56
16
57
16
58
16
59
16
5A
16
5B
16
5C
16
5D
16
5E
16
5F
16
4B
16
4C
16
4D
16
4E
16
4F
16
Address
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Processor mode register 0
Processor mode register 1
One-shot start register
Timer A0 register
Up-down register
Timer A1 register
Register name
Count start register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Access characteristics
WO
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
RW
RW
b7
b0
RW
RW
RW
RW
RW
RW
RW
WO
State immediately after reset
b7
00
16
00
16
00
16
00
16
b0
WO
RW
RW
RW
RW
Timer A0 mode register
(3)
(Note
3)
(3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
RW
RW
Notes 1:
The access characteristics at addresses 4A
16
to 4F
16
vary according to Timer A’s operating
mode. (Refer to
“CHAPTER 8. TIMER A.”
)
2:
The access characteristics at addresses 50
16
to 53
16
vary according to Timer B’s operating
mode.
(Refer to
“CHAPTER 9. TIMER B.”
)
3:
The access characteristics for bit 5 at addresses 5B
16
and 5C
16
vary according to Timer B’s
operating mode. Bit 5 at address 5D
16
is invalid. (Refer to
“CHAPTER 9. TIMER B.”
)
4:
Bit 1 at address 5F
16
becomes “0” immediately after reset. For the M37721S1BFP, fix this bit to
“0.”
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(4)
0 : “0” immediately after reset.
1 : “1” immediately after reset.
:
Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
0
1
0
0
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
State immediately after reset