
7721 Group User’s Manual
11–39
SE R IAL I/ O
11.4 Clock asynchronous serial I/O (UART) mode
Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
selecting 1 stop bit, selecting CTS function)
Fig. 11.4.6 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
selecting 1 stop bit, not selecting CTS function)
Tc
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
SP
D
0
D
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
ST
SP
T
ENDi
TxD
i
T
ENDi
: Next transmit conditions are examined when this signal level is “H.”
(T
ENDi
is an internal signal. Accordingly, it cannot be read from the external.)
Tc: 16(n + 1)/fi or 16(n + 1)/f
EXT
fi: BRGi’s count source frequency (f
2
, f
16
, f
64
, f
512
)
f
EXT
: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
Data is set in UARTi transmit buffer register.
Start bit
Parity bit
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies when
the following conditions are satisfied:
G
Parity enabled
G
1 stop bit
G
CTS function not selected
UARTi transmit register
UARTi transmit buffer register
Stopped because transmit enable bit = “0”
Stop bit
The above timing diagram applies
when the following conditions are
satisfied:
G
Parity enabled
G
1 stop bit
G
CTS function selected
Tc
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
SP
D
0
D
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
SP
ST
T
ENDi
TxD
i
T
ENDi
: Next transmit conditions are examined when this signal level is “H.”
(T
ENDi
is an internal signal. Accordingly, it cannot be read from the external.)
Tc = 16(n + 1)/fi or 16(n + 1)/f
EXT
fi: BRGi’s count source frequency (f
2
, f
16
, f
64
, f
512
)
f
EXT
: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Transfer clock
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
Data is set in UARTi transmit buffer register.
Start bit
Parity
bit
Cleared to “0” when interrupt request is accepted or cleared by software.
UARTi transmit register
Stopped because transmit
enable bit = “0”
Stop
bit
UARTi transmit buffer register
Transmit enable bit
CTSi
Stopped because CTS = “H”