
7721 Group User’s Manual
13-103
DMA CONT R OLLE R
13.9 DMA transfer time
CPU
DMAC
CPU
Right to use
bus
1 block
Array state Transfer
Array state
Transfer
Transition
Termination
Transition
(3)
Array chain transfer mode and Link array chain transfer mode
Fig 13.9.6 Array chain transfer mode and Link array chain transfer mode
Transition of the right to use bus from CPU to DMAC: 1 cycle
Array state:
The number of transfer parameters
×
the number of reads of a transfer parameter
×
the number
of bus cycles for a read + 1 cycle (Refer to
“Table 13.9.1.”
)
DMA transfer per an entire batch of data:
In 2-bus cycle transfer···(Read cycle + Write cycle
C
1
) ×
the number of transfers
C
2
C
1: Add a value which satisfies the read/write conditions. Refer to
“Table 13.4.1.”
C
2: When the transfer unit is 16 bits, the number of transfers = the number of transfer
bytes/2
When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes
In 1-bus cycle transfer···Refer to
“Table 13.4.5.”
Last processing of each block: 3 cycles
Terminate processing: 3 cycles
Transition of the right to use bus from DMAC to CPU: 1 cycle
[Example]
Array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16
bits, the number of transfer blocks = 3, and under the following conditions:
Transfer source: address direction = forward, without Wait
Transfer destination: address direction = backward, without Wait
First block: transfer source’s data start address = even, transfer destination’s data start address
= even, the number of transfer bytes =10 bytes
Second block: transfer source’s data start address = even, transfer destination’s data start address
=odd, the number of transfer bytes =12 bytes
Third block: transfer source’s data start address =odd, transfer destination’s data start address
=odd, the number of transfer bytes =14 bytes
+
+
+
+
+
+
+
+
+
+
= 1 + 19 + 5(2 + 4) + 3 + 19 + 6(2 + 3) + 3 + 19 + 7(4 + 3) + 3 + 1 = 177 cycles