
DMA CONT R OLLE R
13.7 Array chain transfer mode
13-73
7721 Group User’s Manual
b7
b0
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
0 : Wait
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
0 : Wait
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
0 : Data bus D
0
–D
7
or D
0
–D
15
8
15
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
1 : From I/O to memory
AAAAAAAAAAAAAAAAAAA
Transfer direction select bit (Used in 1-bus cycle transfer)
AAAAAAAAAAAAAAAAAAA
DMA2 mode register H (Address 1FED
)
DMA3 mode register H (Address 1FFD
16
)
AAAAAAAAAAAAAAAAAAA
16
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
1 1 : Do not select.
AAAAAAAAAAAAAAAAAAA
0 1 : Forward
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
1 1 : Do not select.
AAAAAAAAAAAAAAAAAAA
0 1 : Forward
AAAAAAAAAAAAAAAAAAA
Transfer source address direction select bits
AAAAAAAAAAAAAAAAAAA
1 : Cycle-steal transfer mode
AAAAAAAAAAAAAAAAAAA
Transfer mode select bit
AAAAAAAAAAAAAAAAAAA
1 : 1-bus cycle transfer
AAAAAAAAAAAAAAAAAAA
Transfer method select bit
AAAAAAAAAAAAAAAAAAA
1 : 8 bits
AAAAAAAAAAAAAAAAAAA
DMA3 mode register L (Address 1FFC
16
)
Number-of-unit-transfer-bits select bit
AAAAAAAAAAAAAAAAAAA
0
AAAAAAAAAAAAAAAAAAA
b7
b0
DMA1 mode register L (Address 1FDC
16
)
AAAAAAAAAAAAAAAAAAA
Selection of transfer mode and each function
AAAAAAAAAAAAAAAAAAA
b7
b0
From preceding “
Figure 13.7.3”
b0
b0
b7
(b7
(b8)
(bb0b7
Set the start address of transfer parameter memory.
These bits can be set to “000000
16
” to “FFFFFF
16
.”
b7
b0
b0
b0b7
b7
(b23)
(b8)
(b16)(b15)
Transfer destination address direction select bits
DMA0 mode register H (Address 1FCD
16
)
Source address register 0 (Addresses 1FC2
16
to 1FC0
16
) (SAR0)
Source address register 1 (Addresses 1FD2
16
to 1FD0
16
) (SAR1)
Source address register 2 (Addresses 1FE2
16
to 1FE0
16
) (SAR2)
Source address register 3 (Addresses 1FF2
16
to 1FF0
16
) (SAR3)
Transfer counter register 0 (Addresses 1FCA
16
to 1FC8
16
) (TCR0)
Transfer counter register 1 (Addresses 1FDA
16
to 1FD8
16
) (TCR1)
Transfer counter register 2 (Addresses 1FEA
16
to 1FE8
16
) (TCR2)
Transfer counter register 3 (Addresses 1FFA
16
to 1FF8
16
) (TCR3)
Set the number of transfer blocks.
These bits can be set to “000001
16
” to “FFFFFF
16
.”
Notes 1:
When writing to these registers,
write to all 24 bits.
2:
Do not write “000000
16
” to TCRi.
DMA0 control register (Address 1FCE
16
)
DMA1 control register (Address 1FDE
16
)
DMA2 control register (Address 1FEE
16
)
DMA3 control register (Address 1FFE
16
)
0 0 0 0 : Do not select.
0 0 0 1 :
External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
Edge sense/Level sense select bit
(Note)
0 : Edge sense
1 : Level sense
DMAACKi validity bit
0 : Invalid
1 : Valid
Note:
When an external source (DMAREQi)
is selected or when the cycle-steal
transfer mode is selected, set this bit
to “0.”
Continue to
“Figure 13.7.5”
on next page.
DMA request source select bits
Fig. 13.7.4 Initial setting example for registers relevant to array chain transfer mode (2)