
13-57
DMA CONT R OLLE R
13.5 Single transfer mode
7721 Group User’s Manual
b7
b0
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
1 : No wait
AAAAAAAAAAAAAAAAAAA
Transfer destination wait bit
(Valid in DMA transfer)
AAAAAAAAAAAAAAAAAAA
1 : No wait
AAAAAAAAAAAAAAAAAAA
1 : Data bus D
8
–D
15
AAAAAAAAAAAAAAAAAAA
0
7
0
15
AAAAAAAAAAAAAAAAAAA
I/O connection select bit (Valid in 1-bus cycle transfer)
AAAAAAAAAAAAAAAAAAA
0 : From memory to I/O
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
0
0
0
0
DMA1 mode register H (Address 1FDD
16
)
DMA2 mode register H (Address 1FED
16
)
AAAAAAAAAAAAAAAAAAA
16
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
1 0 : Backward
1 1 : Do not select.
AAAAAAAAAAAAAAAAAAA
0 0 : Fixed
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
1 0 : Backward
AAAAAAAAAAAAAAAAAAA
0 0 : Fixed
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
0 : Burst transfer mode
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
0 : 2-bus cycle transfer
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
1 : 8 bits
AAAAAAAAAAAAAAAAAAA
Number-of-unit-transfer-bits select bit
AAAAAAAAAAAAAAAAAAA
0
DMA3 mode register L (Address 1FFC
16
)
AAAAAAAAAAAAAAAAAAA
b7
b0
DMA0 mode register L (Address 1FCC
)
DMA1 mode register L (Address 1FDC
16
)
AAAAAAAAAAAAAAAAAAA
Selection of transfer mode and each function
From preceding “
Figure 13.5.2”
b0
b0
b7
(b7
(b8)
(bb0b7
Set the transfer start address of transfer source.
These bits can be set to “000000
16
” to “FFFFFF
16
.”
b0
b0
b7
(b7
(b8)
(bb0b7
b7
b0
b0
b0b7
b7
(b23)
(b8)
(b16)(b15)
Transfer source wait bit
(Valid in DMA transfer)
Selection of single transfer mode
Source address register 0 (Addresses 1FC2
16
to 1FC0
16
) (SAR0)
Source address register 1 (Addresses 1FD2
16
to 1FD0
16
) (SAR1)
Source address register 2 (Addresses 1FE2
16
to 1FE0
16
) (SAR2)
Source address register 3 (Addresses 1FF2
16
to 1FF0
16
) (SAR3)
Destination address register 0 (Addresses 1FC6
16
to 1FC4
16
) (DAR0)
Destination address register 1 (Addresses 1FD6
16
to 1FD4
16
) (DAR1)
Destination address register 2 (Addresses 1FE6
16
to 1FE4
16
) (DAR2)
Destination address register 3 (Addresses 1FF6
16
to 1FF4
16
) (DAR3)
Set the transfer start address of destination.
These bits can be set to “000000
16
” to “FFFFFF
16
.”
Transfer counter register 0 (Addresses 1FCA
16
to 1FC8
16
) (TCR0)
Transfer counter register 1 (Addresses 1FDA
16
to 1FD8
16
) (TCR1)
Transfer counter register 2 (Addresses 1FEA
16
to 1FE8
16
) (TCR2)
Transfer counter register 3 (Addresses 1FFA
16
to 1FF8
16
) (TCR3)
Set the byte number of transfer data.
These bits can be set to “000001
16
” to “FFFFFF
16
.”
Notes 1:
When writing to these registers,
write to all 24 bits.
2:
Do not write “000000
16
” to TCRi.
Note 3:
When data is transferred from memory to I/O in 1-bus
cycle transfer, it is unnecessary to set DARi.
When data is transferred form I/O to memory in 1-bus
cycle transfer, it is unnecessary to set SARi.
DMA0 control register (Address 1FCE
16
)
DMA1 control register (Address 1FDE
16
)
DMA2 control register (Address 1FEE
16
)
DMA3 control register (Address 1FFE
16
)
0 0 0 0 : Do not select.
0 0 0 1 :
External source (DMAREQi)
0 0 1 0 : Software DMA source
0 0 1 1 : Timer A0
0 1 0 0 : Timer A1
0 1 0 1 : Timer A2
0 1 1 0 : Timer A3
0 1 1 1 : Timer A4
1 0 0 0 : Timer B0
1 0 0 1 : Timer B1
1 0 1 0 : Timer B2
1 0 1 1 : UART0 receive
1 1 0 0 : UART0 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : UART1 transmit
1 1 1 1 : A-D conversion
Edge sense/Level sense select bit
(Note)
0 : Edge sense
1 : Level sense
DMAACKi validity bit
0 : Invalid
1 : Valid
Note:
When an external source (DMAREQi)
is selected or when the cycle-steal
transfer mode is selected, set this bit
to “0.”
Continue to
“Figure 13.5.4”
on next page.
DMA request source select bits
Fig. 13.5.3 Initial setting example for registers relevant to single transfer mode (2)