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SE R IAL I/ O
7721 Group User’s Manual
11–14
11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers
When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be
used. Each interrupt has its corresponding interrupt control register. Figure 11.2.12 shows the structure of
UARTi transmit interrupt control and UARTi receive interrupt control registers.
For details about interrupts, refer to
“CHAPTER 7. INTERRUPTS.”
11.2 Block description
Fig. 11.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers
(1)
Interrupt priority level select bits (bits 0 to 2)
These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When
using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi
transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt
priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the
IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable UARTi
transmit/receive interrupts, set these bits to “000
2
” (level 0).
(2)
Interrupt request bit (bit 3)
The UARTi transmit interrupt request bit is set to “1” when data is transferred from the UARTi
transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit is set
to “1” when data is transferred from the UARTi receive register to the UARTi receive buffer register.
(However, when an overrun error occurs, it does not change.)
Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request is
accepted. This bit can be set to “1” or “0” by software.
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit interrupt control register (Address 71
16
)
UART0 receive interrupt control register (Address 72
16
)
UART1 transmit interrupt control register (Address 73
16
)
UART1 receive interrupt control register (Address 74
16
)
Bit
7 to 4
Interrupt request bit
2
1
0
Bit name
At reset
0
RW
Functions
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Low level
High level
b2 b1 b0
0 : No interrupt requested
1 : Interrupt requested
Interrupt priority level select bits
3
RW
RW
RW
RW
–
Undefined
0
0
0
Nothing is assigned.