參數(shù)資料
型號: LXT6155LE
元件分類: 通信、網(wǎng)絡模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 41/48頁
文件大?。?/td> 1105K
代理商: LXT6155LE
Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
41
PLL lock time
Tlock
100
μ
s
PRBS(23) pattern, from data
applied at RTIP/RRING.
Device in fiber optic mode.
Equalizer adaptation time
500
bits
From data applied
Line input impedance
(RTIP and RRING)
RIN
4
k
Differential resistance
Table 33. Serial Control Timing
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions
1
Rise/Fall time - All TTL outputs
tRF
25
ns
Load 1.6 mA, 50 pF
SDI to SCLK setup time
tDC
5
ns
SCLK to SDI hold time
tCDH
5
ns
SCLK low time
tCL
120
ns
SCLK high time
tCH
120
ns
SCLK rise and fall time
tR, tF
25
ns
CS to SCLK setup time
tCC
5
ns
SCLK to CS hold time
tCCH
5
ns
CS inactive time
tCWH
5
ns
SCLK to SDO valid
tCDV
0
20
ns
SCLK falling edge to SDO high Z
tCDZ
0
20
ns
CS rising edge to SDO high Z
tCZ
0
20
ns
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to
production testing.
Figure 22. Microprocessor Input Timing Diagram
Table 32. Receive Analog Characteristics (Continued)
Parameter
Note
Min
Typ
1
Max
Unit
Test Conditions
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to production
testing.
2. Not production tested, guaranteed by design and other correlation factors.
CS
t
CWH
t
CCH
t
CL
t
CH
t
CC
SCLK
SDI
t
DC
R/W
t
CDH
CONTROL BYTE
DATA BYTE
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