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| 型號： | LXT6155LE |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | LXT6155LE |
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Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
13
2.1.1
Transmitted Signal
Transmitted signals conform to the standard templates listed in
Table 2
.
2.1.1.1
Fiber Based G.957/GR-253 Transmission Systems
The Intel
LXT6155 provides 3.3 V LVPECL compatible signals for interfacing to a fiber optic
transceiver. Please refer to Application Information for interface schematics.
2.1.2
Coax Based G.703/GR-253 Transmission Systems
The Intel
LXT6155 encodes and decodes CMI signals that are transmitted onto a 75
coax cable
compliant with STM1/STS-3 CMI templates. Please refer to the CMI templates shown in
Figure 24
and
Figure 25
.
2.1.2.1
CMI Encoding
Coded Mark Inversion (CMI) is an encoding scheme adopted by SONET STS-3 and SDH STM1
standards. CMI encoding guarantees at least one transition per bit, thereby enhancing the clock
recovery process. CMI encodes a “0” with a midpoint positive transition, and a “1” as Low or
High, in opposite polarity to the previous encoded “1”. Refer to
Figure 7
,
Figure 24
and
Figure 25
for encoding and pulse template information.
2.1.3
Tx Clock Monitoring
The Intel
LXT6155 provides transmit clock monitoring for both serial and parallel operating
modes. When using the crystal clock as a reference, the Intel
LXT6155 monitors the TSICLKP/
TSICLKN or the TPICLK input(s) for transitions. If no transition is seen within 200 ns, the
tx_clk_alarm flag will be set (reg #15) and the transmitter outputs ttip1/tring1 or ttip0/tring0 will
stop sending data to the line. This condition will remain until the Intel
LXT6155 detects clock
transitions at the transmitter input(s) TSICLKP/TSICLKN or TPICLK. Transmit clock monitoring
can be disabled in software mode only.
Figure 3. Intel
LXT6155 System Interface
Tx
Rx
μ
Processor
(optional)
LXT6155
4
Fiber Optic Modules
or Coax Transformers
2
2
SONET/SDH
Overhead
Terminator
ATM UNI
1
2
1
2
Data/Clock (8-bit parallel or serial mode)
Data/Clock (8-bit parallel or serial mode)
Receive Output Frame Pulse (ROFP)
Receive Ouput PLL Lock (LOCK)
Loss of Signal (LOS)
System Interface
Line Interface
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