參數(shù)資料
型號(hào)： LXT6155LE
元件分類(lèi)： 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁(yè)數(shù)： 19/48頁(yè)
文件大?。?/td> 1105K
代理商： LXT6155LE
Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
19
2.4.2
Jitter Generation (Intrinsic Jitter)
Jitter generation is the amount of transmit jitter at the output of the equipment with a jitter-free
transmit input data and clock. For SONET/SDH, jitter generation is less than 0.01 UI rms,
measured with a band-pass filter from 12 kHz to 1.3 MHz. Refer to Figure 27 on page 45 for the
Intel
LXT6155 performance.
2.4.3
Jitter Transfer
Jitter transfer is defined as the ratio of output jitter to input jitter amplitude versus jitter frequency
for a given bit rate. Input jitter amplitude is shown in the Jitter Tolerance curve. Output jitter is
under the Jitter Transfer template. Refer to Figure 27 on page 45 and Figure 28 on page 45 for the
Intel
LXT6155 performance.
2.5
Operational Modes
The Intel
LXT6155 functions in both Hardware standalone and Software modes. The operating
mode is set by the state of the HWSEL pin.
2.5.1
Hardware Mode
By setting HWSEL = Low, the Intel
LXT6155 operates in standalone hardware mode, without a
serial microprocessor interface. A subset of the functions available in the Software Mode can be set
in Hardware Mode. Intel
LXT6155 provides a comprehensive flexibility in configuring system
clock preference settings, as well as providing pins for activating loopback test modes.
Table 3
,
Table 4
and
Table 5
show the settings that enable the functions available in hardware mode.
Figure 8. Hardware Mode
Nevada
HWSEL
MODE
RLIS
CIS
SP
GND
Line interface encode/
decode
Remote loopback
Serial/Parallel
Clock reference select
Local loopback
LLIS
RIFE
Frame Enable
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