
Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
15
2.2.2
Receive Frame Detect and Byte Alignment
Receive Frame Detection only operates in parallel mode, if Frame Detection is enabled. The Intel
LXT6155 provides aligned bytes RPOD<7:0> following the distinct SONET OC3/STM1 frame
marker word, 3 x A1, followed by 3 x A2, where A1=F6h and A2=28h. The Receive Output Frame
Pulse (ROFP) asserts during the third A2 byte, and de-asserts after one complete RPOCLK clock
period. If this feature is used, it can be enabled in register #12 bit <3> in software mode
1
, or by
setting the RIFE (pin 15) high in hardware mode prior to applying data to Rtip/Rring. Two
consecutive frames with correct frame words (A
1
… A
1
A
2
…A
2
) are required to change from an
out-of-frame state (OOF) to an in-frame state. The OOF alarm is accessible in SW mode (HWSEL
= High) as a status or interrupt signal (Reg #15). To declare an OOF condition, four consecutive
frames with incorrect frame words are required. Byte alignment occurs when entering the in-frame
state. In case of an OOF event, the byte alignment and frame pulse position are frozen. The ROFP
output continues unchanged until re-entering the in-frame state.
2.2.2.1
Loss of Signal (LOS)
Loss of Signal provides an alarm signal indicating incoming signal voltage is weak or incoming
data does not contain enough transitions. This signal is available in HW mode on pin #45 and in
SW mode as status and interrupt (Reg #15, modes 00 and 05).
2.2.2.2
Coax Interface
Loss of Signal provides an alarm output that indicates weak line input signal. The LOS signal
asserts when the incoming signals fall below a specified loss threshold, and de-asserts when the
line signal rises nominally 2 dB above the assert threshold. The threshold is adjustable in SW mode
(HWSEL = High) via the
μ
Processor interface.
2.2.2.3
Fiber Interface
If no transition is detected during any 3112 bit times (20
μ
sec), LOS asserts. LOS is cleared when
two consecutive frame words with no LOS events between then are received. In SW mode
(HWSEL = High) the assertion window is programmable from 128 bits to 4096 bits in four steps.
The deassertion criteria can also be configured to 12.5% transition density. The 12.5% density is
determined by receipt of at least 4 transitions during a 32-bit sliding window.
1. For further details see register #12 description for usage.
Figure 4. Framing State
In Frame
4 consecutive frames
with errored FAS
2 consecutive frames
with correct FAS
Out of Frame