參數(shù)資料
型號(hào)： LXT6155LE
元件分類(lèi)： 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁(yè)數(shù)： 17/48頁(yè)
文件大小： 1105K
代理商： LXT6155LE
Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Datasheet
17
2.3
Clocks
2.3.1
Parallel Mode
The Intel
LXT6155 accepts TPICLK synchronized with transmit input parallel data TPID<7:0>.
The data is serialized and transmitted at TTIP0/TRING0 or TTIP1/TRING1 depending on which
line encoding mode is selected. The Intel
LXT6155 in turn produces the receive output parallel
clock RPOCLK, that is recovered from incoming line data RTIP/RRING, and is synchronized with
receive output parallel data RPOD<7:0>.
2.3.1.1
Transmit Parallel Input Clock (TPICLK)
TPICLK is the transmit parallel input clock provided by the systems interface. This clock must be
nominally 19.44 MHz, synchronized with parallel input data TPID<7:0>. This clock is then
internally multiplied by 8 to produce a serial clock, used for parallel-to-serial conversion, line
drivers, and pulse reshaping. In HW mode (HWSEL = Low), TPID data is sampled on the falling
edge of TPICLK. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit
#3).
2.3.1.2
Receive Parallel Output Clock (RPOCLK)
RPOCLK is the parallel output clock that is recovered from the line input data RTIP/RRING. This
clock is at 19.44 MHz, synchronized with parallel output data RP0D<7:0>. In HW mode (HWSEL
= Low), the RPOCLK clock rising edge is at the center of eye opening of RPOD<7:0> as shown in
Figure 21
. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit #2).
Under LOS (LOS=High) or Rx PLL loss of lock (LOCK=Low) conditions RPOCLK is switched to
the reference selected by the CIS control in HW mode, or Reg #0 bit #5 in SW mode. Also, the
parallel output is forced to all zeros. This feature can be disabled in SW mode (HWSEL = High)
via register #10, bit #7.
Figure 7. Example of CMI Encoded Binary Signal
0
0
0
1
1
1
1
Binary
CMI
T/2
T/2
T
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