參數(shù)資料
型號: LXT6155LE
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 40/48頁
文件大小: 1105K
代理商: LXT6155LE
Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
40
Datasheet
Figure 21. Receive Parallel Output Data Timing
(See
Table 31
)
Table 32. Receive Analog Characteristics
Parameter
Note
Min
Typ
1
Max
Unit
Test Conditions
End to end loss budget (coax)
1
-
15
dB
BER=1E-12. PRBS (23) data.
CMI encoded. Input white
noise = 5 mV RMS max.
LOS - fiber
Assert
20
μ
sec
No data transition. Default
LOS setting.
De-assert
187.5
μ
sec
No LOS events. Default LOS
settings.
LOS Thresholds - Coax
Assert
18
dB
Attenuation measured at
78 MHz, CMI, 75
load.
12.7 dB cable loss plus
remaining flat loss.
De-assert
17
dB
LOS hysteresis - coax
HYS
1.0
4.0
dB
Measured from the level
where LOS is asserted.
PRBS(23) data.
Receive jitter generation
2
(intrinsic jitter SONET spec)
12 kHz - 1.3 MHz
0.01
UIrms
CMI encoded PRBS(23) at
RTIP/RRING with no data
jitter. Transmit input = all
zeros Refer to
Figure 27
and
Table 35
.
0.1
UIpp
Receive jitter generation
2
(intrinsic jitter SDH spec)
500 Hz - 1.3 MHz
1.5
UIpp
65 kHz - 1.3 MHz
0.075
UIpp
Receive jitter transfer peaking
2
DC - 230 kHz
0.4
dB
PRBS(23) Data. Input jitter as
the max. tolerance curve
shown in
Figure 26
.
Receive jitter tolerance
2
0.1 Hz - 19.3 Hz
39
UIpp
BER=1E-10. Tolerated jitter
meets
Figure 26
500 Hz - 6.5 kHz
1.5
UIpp
65 kHz -
0.15
UIpp
PLL nominal center frequency
Fnom
155.5
2
MHz
PLL capture range
Fcap
-20
+20
ppm
PLL track range
Ftrack
-20
+20
ppm
1. Typical values are at 25 C and 3.3 V. They are for design aid only; not guaranteed and not subject to production
testing.
2. Not production tested, guaranteed by design and other correlation factors.
RPOCLK*
RPOD<0:7>
ROFP
RPOCLKPD
ROFPPD
*This shows timing in HW mode. In SW mode (HWSEL=1) this clock polarity can be inverted. See Table 8 for details.
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