參數(shù)資料
型號： LXT6155LE
元件分類： 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁數(shù)： 18/48頁
文件大小： 1105K
代理商： LXT6155LE
Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
18
Datasheet
2.3.2
Serial Mode
At the transmit systems interface, the Intel
LXT6155 accepts the transmit input clock TSICLKP/
TSICLKN that is synchronized to incoming serial differential data TPOS/TNEG. At the line
interface, the Intel
LXT6155 accepts RTIP/RRING data and produces the clocks RSOCLKP/
RSOCLKN synchronized to receive output data RPOS/RNEG. RSOCLKP/RSOCLKN clock edges
are at the center of RPOS/RNEG.
2.3.2.1
Transmit Serial Input Clock (TSICLKP/TSICLKN)
TSICLKP/TSICLKN is the serial input clock from the overhead terminator. This 155.52 MHz
clock is rising edge centered with input serial data on TPOS and TNEG. These clock pins should be
left open when the Intel
LXT6155 operates in parallel mode.
2.3.2.2
Receive Serial Output Clock (RSOCLKP/RSOCLKN)
RSOCLKP/RSOCLKN is the serial clock recovered from the line input data on RTIP/RRING. This
155.52 MHz clock is falling edge centered with receive serial output data on RPOS/RNEG. These
clock pins should be left open when the Intel
LXT6155 operates in parallel mode. Under LOS
(LOS=High) or Rx PLL loss of lock (LOCK=Low) conditions RSOCLK P/N is switched to the Tx
serial clock. Also the serial output data is forced to all zeros. This feature can be disabled in SW
mode (HWSEL = High) via register #10, bit #7.
2.3.3
Crystal Reference Clock (XTALIN/XTALOUT)
An optional 19.44 MHz crystal can be connected across the XTALIN and XTALOUT pins. This
crystal reference provides an onchip clock that is independent of the external system clock
(TSICLKP/TSICLKN or TPICLK). The main functions of the crystal reference clock are threefold:
(1) to center the receive PLL at 155 MHz, (2) to keep the PLL centered at 155 MHz when LOS
asserts, and (3) In the event incoming data is lost, to provide a reference clock for other devices
which require it. The designer has the option to use this crystal reference clock or the transmit input
clock (TSICLKP/TSICLKN or TPICLK) to center the receive PLL.
2.4
Jitter
The Bellcore GR-253 standard defines jitter as the “short-term variations of a digital signal’s
significant instants from their ideal positions in time”. Significant instants are the optimum data
sampling instants. Jitter parameters can be measured at the line interface, with system interface in
loopback mode, yielding jitter accumulated in both transmitter and receiver. Isolated jitter
measurements for transmitter and receiver can also be performed. Jitter specs are divided into three
categories: jitter tolerance, jitter generation, and jitter transfer. Jitter values, in effect, measure the
performance of the receive PLL and the transmit synthesizer PLL.
2.4.1
Jitter Tolerance
Jitter tolerance is the peak-to-peak amplitude of sinusoidal jitter applied at the line interface input
that causes an equivalent 1 dB SNR loss measured as BER = 10
-10
. Refer to Figure 26 on page 44
for the Intel
LXT6155 performance.
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