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參數(shù)資料
| 型號： | LXT6155LE |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | LXT6155LE |
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Intel
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
14
Datasheet
In remote loopback, transmit clock monitoring is disabled in SW and HW mode. In SW mode,
when using transmit clocks as the receive PLL reference, the user must disable transmit clock
monitoring by setting reg #1 bit <0> low.
2.2
Receiver
2.2.1
Analog Front End and Timing Recovery
2.2.1.1
CMI Mode
Received data on RTIP/RRING goes through an adaptive equalizer. An adaptive
adaptive Automatic Gain Control (AGC) compensate the frequency-and-cable length dependent
loss in data signal, and reshapes the signal to the optimal waveform. A Phase Locked Loop (PLL)
then performs clock recovery operation, comparing the reshaped data phase against the receive
output clock phase. The receive PLL requires an external reference (e.g. transmit input clock or
XTAL clock) to start up the clock recovery process. This clock can be derived from XTALIN,
TPICLK or TSICLK (
÷
8). The recovered clock is used to retime the CMI signals, and to decode
CMI to NRZ. Coding errors are detected and flagged via the CMIERR pin in HW mode with the
frame detect disabled or in serial mode. In software mode (HWSEL = High) CMI coding errors are
indicated via the
μ
P interface interrupt register: Reg #15, mode 05.
equalizer and
2.2.1.2
NRZ Mode
The on chip adaptive equalizer is bypassed. Data goes straight to the clock recovery phase locked
loop. The PLL then performs clock recovery operation, comparing the data phase against the clock
phase. This clock can be derived from XTALIN, TPICLK or TSICLK (
÷
8). The receive PLL
requires an external reference (e.g. transmit input clock or XTAL clock) to start up the clock
recovery process.
The recovered clock is used to retime the data signals. When the recovered clock is within 488 ppm
of the reference clock, the LOCK signal asserts. This alarm is also accessible on the
μ
P interface as
a status bit (Reg #15, mode 0) and as an interrupt (Reg #15, mode 05). Once the recovered clock
has been obtained and the NRZ data has been recovered, the Intel
LXT6155 performs frame-
detect-and-byte-alignment, and serial-to-parallel conversion. The Intel
LXT6155 optionally
provides output data RPOD<7:0> aligned to the SDH/SONET byte boundary. The user has the
option to enable/disable the frame-alignment function in both hardware and software mode. The
frame detect/byte alignment function generates the receive output frame pulse (ROFP). In HW
mode (HWSEL = Low) ROFP asserts (high) on the third A2 byte. In SW mode (HWSEL = High)
this position is programmable via register #13, bits <6:3>. When byte alignment is disabled and the
Intel
LXT6155 is in CMI mode, the ROFP pin indicates CMI coding errors including polarity
errors for ones and inversion errors for zeroes.
The clock recovery PLL’s center frequency comes from either the local crystal or a stable transmit
input clock (TSICLKP/TSICLKN or TPICLK). If operated in loop-timed mode or remote loopback
mode, an external reference clock must be used to center the internal PLL clock. In remote
loopback, the receive reference remains either XTALIN or TSICLK or TPICLK, depending on the
control selection. If an independent and stable transmit clock is available, the designer has the
option of applying this clock to pin XTALIN to center the PLL, without the external crystal.
The user can also replace the crystal by connecting the TPICLK (19.44 MHz) signal to the
XTALIN pin. However, a local crystal is recommended for “keep alive” purposes in case the clock
becomes unavailable.
f
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