參數(shù)資料
型號: LPC2368FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: ARM7 with 512 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, SD-MMC, and 10-bit ADC
封裝: LPC2368FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 8/18頁
文件大?。?/td> 220K
代理商: LPC2368FBD100
ES_LPC2368
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 20 April 2011
8 of 18
NXP Semiconductors
ES_LPC2368
Errata sheet LPC2368
3.7 PLL.1: PLL output (F
CCO
) is limited to 290 MHz
Introduction:
The PLL input, in the range of 32 KHz to 50 MHz, may initially be divided down by a value
“N”, which may be in the range of 1 to 256. Following the PLL input divider is the PLL
multiplier. This can multiply the input divider output through the use of a Current
Controlled Oscillator (CCO) by a value “M”, in the range of 1 through 32768. The resulting
frequency, F
CCO
must be in the range of 275 MHz to 550 MHz.This frequency can be
divided down (using the Clock Divider registers) to get the desired clock frequencies for
the core and peripherals.
Problem:
The maximum output of the CCO within the PLL block is limited to 290 MHz.
Work-around:
Care should be taken while programming the PLL so that F
CCO
resides in the desired
range. The suggested setting is to use a 12 MHz external crystal. Use a PLLdivider (N) of
1 and PLL multiplier (M) of 12. Putting the values in the equation:
F
CCO
= (2
M
FIN) / N
F
CCO
= 288 MHz
The CPU Clock Configuration register (located at 0xE01F C104) can then be used to
divide this frequency by 4 to produce the maximum CPU speed of 72 MHz (except on Rev
‘-’ and Rev ‘A’, see Flash.1).
3.8 SRAM.1: 16 kB SRAM cannot be used for code execution
Introduction:
The LPC2368 has 16 kB of SRAM on the AHB2 bus, which would generally be used by
the Ethernet block.
Problem:
The 16 kB of SRAM can only be used as data RAM. Code can not be executed from this
memory.
Work-around:
No known workaround.
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