參數(shù)資料
型號(hào): LPC2368FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: ARM7 with 512 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, SD-MMC, and 10-bit ADC
封裝: LPC2368FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 220K
代理商: LPC2368FBD100
ES_LPC2368
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 20 April 2011
4 of 18
NXP Semiconductors
ES_LPC2368
Errata sheet LPC2368
Deep
power-down.1
VBAT.1
Deep power-down mode is not functional
‘-’, ‘A’, ‘B’
Section 3.17 on page 13
Increased power consumption on VBAT when VBAT is
powered before the 3.3 V supply used by rest of device
The VBAT pin cannot be left floating
External sync inputs not operational
‘-’, ‘A’, ‘B’
Section 3.18 on page 13
VBAT.2
ADC.2
‘-’, ‘A’, ‘B’
‘-’, ‘A’, ‘B’, ‘D’
Section 3.19 on page 13
Section 3.20 on page 14
Table 2.
Functional
problems
Functional problems table
…continued
Short description
Revision identifier
Detailed description
Table 3.
AC/DC
deviations
ESD.1
AC/DC deviations table
Short description
Product version(s)
Detailed description
2 kV ESD requirements are not met on the RTCX1 pin
‘-’
Section 4.1 on page 15
Table 4.
Errata notes
Note.1
Errata notes table
Short description
When the input voltage is Vi
V
DD
I/O + 0.5 V on each
of the following port pins P0.23, P0.24. P0.25, P0.26,
P1.30, and P1.31 (configured as general purpose input
pin (s)), current must be limited to less than 4 mA by
using a series limiting resistor.
On the LPC2368 Rev D, design changes to the
Memory Accelerator Module were made to enhance
timing and general performance.
Revision identifier
‘-’, ‘A’, ‘B’, ‘D’
Detailed description
Section 5.1 on page 15
Note.2
‘D’
Section 5.2 on page 15
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