參數(shù)資料
型號: LPC2368FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: ARM7 with 512 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, SD-MMC, and 10-bit ADC
封裝: LPC2368FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 11/18頁
文件大小: 220K
代理商: LPC2368FBD100
ES_LPC2368
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 20 April 2011
11 of 18
NXP Semiconductors
ES_LPC2368
Errata sheet LPC2368
3.14 Flash.1: Operating speed out of on-chip flash is restricted
Introduction:
The operating speed of this device out of internal flash/SRAM is specified at 72 MHz.
Problem:
Code execution from internal flash is restricted depending upon the device revision:
1. Rev ‘A’ devices: Code execution from internal flash is restricted to a maximum of
60 MHz.
For example, use a PLL output frequency of F
CCO
= 360 MHz and divide it by 6
(CCLKSEL = 5) to generate 60 MHz CPU clock (do not use even values for CCLKSEL).
2. Rev ‘-’ devices: Code execution from internal flash is restricted to a maximum of
60 MHz also.
However, this device revision has one more restriction in terms of the PLL output
frequency (F
CCO
- Please refer to PLL.1 above). F
CCO
is limited to 290 MHz.
Considering the same example in PLL.1 (Input crystal-12 MHz, N = 1, M = 12):
F
CCO
= 288 MHz
The CPU Clock Configuration register (located at 0xE01F C104) can then be used to
divide this frequency by 6 (CCLKSEL = 5) to achieve 48 MHz. Since this register only
accepts odd values for CCLKSEL, a division by 5 (CCLKSEL = 4) is not a valid option.
In both the above revisions, code can still execute out of SRAM at up to 72 MHz.
Work-around:
None.
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