參數(shù)資料
型號(hào): LPC2368FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: ARM7 with 512 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, SD-MMC, and 10-bit ADC
封裝: LPC2368FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 15/18頁
文件大小: 220K
代理商: LPC2368FBD100
ES_LPC2368
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 20 April 2011
15 of 18
NXP Semiconductors
ES_LPC2368
Errata sheet LPC2368
4. AC/DC deviations detail
4.1 ESD.1: The LPC2368 does not meet the 2 kV ESD requirements on the
RTCX1 pin
Introduction:
The LPC2368 is rated for 2 kV ESD. The RTCX1 pin is the input pin for the RTC oscillator
circuit.
Problem:
The LPC2368 does not meet the required 2 kV ESD specified.
Work-around:
Observe proper ESD handling precautions for the RTCX1 pin.
5. Errata notes detail
5.1 Note.1
On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when
configured as general purpose input pin (s)), leakage current increases when the input
voltage is Vi
V
DD
I/O + 0.5 V. Care must be taken to limit the current to less than 4 mA by
using a series limiting resistor.
5.2 Note.2
On the LPC2368 Rev D, design changes to the Memory Accelerator Module were made
to enhance timing and general performance. Design changes are intended to enhance
performance in general and will result in minor differences in the code execution timing
between the previous device revisions and rev D. Actual performance impact is code
dependent, some code sequences may speed up while other code sequences may slow
down between the previous device revisions and rev D. This might be observed when
using software delays and in such cases, a hardware timer should be used to generate a
delay instead of a software delay.
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