參數(shù)資料
型號: LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁數(shù): 6/74頁
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
6 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2.
Pin configuration LQFP80 package
60
2
4
8
6
41
1
20
002aae158
Table 3.
Symbol
P0[0] to P0[31]
Pin description
Pin
Type
I/O
Description
Port 0:
Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of Port 0 pins depends upon the pin function selected via the pin
connect block. Some port pins are not available on the LQFP80 package.
P0[0] —
General purpose digital input/output pin.
RD1 —
CAN1 receiver input.
TXD3 —
Transmitter output for UART3.
SDA1 —
I
2
C1 data input/output (this is not an I
2
C-bus compliant open-drain pin).
P0[1] —
General purpose digital input/output pin.
TD1 —
CAN1 transmitter output.
RXD3 —
Receiver input for UART3.
SCL1 —
I
2
C1 clock input/output (this is not an I
2
C-bus compliant open-drain pin).
P0[2] —
General purpose digital input/output pin.
TXD0 —
Transmitter output for UART0.
AD0[7] —
A/D converter 0, input 7.
P0[3] —
General purpose digital input/output pin.
RXD0 —
Receiver input for UART0.
AD0[6] —
A/D converter 0, input 6.
P0[6] —
General purpose digital input/output pin.
I2SRX_SDA —
Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the
I
2
S-bus specification
.
(LPC1759/58/56 only).
SSEL1 —
Slave Select for SSP1.
MAT2[0] —
Match output for Timer 2, channel 0.
P0[0]/RD1/TXD3/
SDA1
37
[1]
I/O
I
O
I/O
I/O
O
I
I/O
I/O
O
I
I/O
I
I
I/O
I/O
P0[1]/TD1/RXD3/
SCL1
38
[1]
P0[2]/TXD0/AD0[7] 79
[2]
P0[3]/RXD0/AD0[6] 80
[2]
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
64
[1]
I/O
O
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