參數(shù)資料
型號(hào): LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁(yè)數(shù): 50/74頁(yè)
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
50 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
11.5 I
2
C-bus
Table 12.
T
amb
=
40
C to +85
C.
[2]
Symbol
f
SCL
[1]
See the I
2
C-bus specification
UM10204
for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
t
HD;DAT
is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
V
IH
(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
C
b
= total capacitance of one bus line in pF.
The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage t
f
is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
f
.
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[5]
[6]
[7]
[8]
The maximum t
HD;DAT
could be 3.45
s and 0.9
s for Standard-mode and Fast-mode but must be less than
the maximum of t
VD;DAT
or t
VD;ACK
by a transition time (see the I
2
C-bus specification
UM10204
). This
maximum must only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9]
t
SU;DAT
is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
Dynamic characteristic: I
2
C-bus pins
[1]
Parameter
SCL clock
frequency
Conditions
Standard-mode
Fast-mode
of both SDA and
SCL signals
Standard-mode
Fast-mode
Standard-mode
Fast-mode
Standard-mode
Fast-mode
Standard-mode
Fast-mode
Standard-mode
Fast-mode
Min
0
0
-
Max
100
400
300
Unit
kHz
kHz
ns
t
f
fall time
[4][5][6][7]
20 + 0.1
C
b
4.7
1.3
4.0
0.6
0
0
250
100
300
-
-
-
-
-
-
-
-
ns
s
s
s
s
s
s
ns
ns
t
LOW
LOW period of
the SCL clock
t
HIGH
HIGH period of
the SCL clock
t
HD;DAT
data hold time
[3][4][8]
t
SU;DAT
data set-up
time
[9]
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