參數(shù)資料
型號: LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁數(shù): 5/74頁
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
5 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
Grey-shaded blocks represent peripherals with connection to the GPDMA.
Fig 1.
Block diagram
SRAM
64/32/
16/8 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
E
T
FLASH
ACCELERATOR
FLASH
512/256/128/64/32 kB
DMA
CONTROLLER
ETHERNET
CONTROLLER
WITH DMA
(2)
USB HOST/
DEVICE/OTG
CONTROLLER
WITH DMA
(4)
I-code
bus
D-code
bus
system
bus
AHB TO
APB
BRIDGE 0
HIGH-SPEED
GPIO
AHB TO
APB
BRIDGE 1
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTAL1
XTAL2
RESET
clocks and
controls
JTAG
interface
debug
port
USB PHY
SSP0
UART2/3
I2S
(1)
RI TIMER
SYSTEM CONTROL
SSP1
UART0/1
CAN1/CAN2
(1)
I2C1
TIMER 0/1
WDT
PWM1
12-bit ADC
PIN CONNECT
GPIO INTERRUPT CONTROL
RTC
BACKUP REGISTERS
32 kHz
OSCILLATOR
APB slave group 1
APB slave group 0
RTC POWER DOMAIN
LPC1759/58/56/54/52/51
master
master
master
002aae153
slave
slave
slave
slave
ROM
slave
slave
MULTILAYER AHB MATRIX
P0, P1,
P2, P4
SCK0
SSEL0
MISO0
MOSI0
RXD2/3
TXD2/3
I2SRX_SDA
I2STX_CLK
I2STX_WS
I2STX_SDA
TX_MCLK
RX_MCLK
SCK1
SSEL1
MISO1
MOSI1
SCL2
SDA2
I2C2
MOTOR CONTROL PWM
MCOA[2:0]
MCOB[2:0]
MCI[2:0]
PHA, PHB
INDEX
TIMER2/3
4
×
MAT2
2
×
MAT3
DAC
(3)
AOUT
QUADRATURE ENCODER
RTCX1
RTCX2
VBAT
PWM1[6:1]
PCAP1[1:0]
2
×
MAT0/1
1
×
CAP0,
2
×
CAP1
RD1/2
TD1/2
SCL1
SDA1
AD0[7:2]
SCK/SSEL
MOSI/MISO
8
×
UART1
RXD0/TXD0
P0, P2
RMII pins
USB pins
M
(1)
LPC1759/58/56 only
(2)
LPC1758 only
EXTERNAL INTERRUPTS
EINT0
(3)
LPC1759/58/56/54 only
(4)
LPC1752/51 USB device only
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