- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385496 > LPC1751FBD80 (NXP SEMICONDUCTORS) Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | LPC1751FBD80 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC |
| 中文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN |
| 文件頁數(shù)： | 18/74頁 |
| 文件大小： | 1572K |
| 代理商： | LPC1751FBD80 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
18 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can
be programmed to generate an interrupt on a rising edge, a falling edge, or both. The
edge detection is asynchronous, so it may operate when clocks are not present such as
during Power-down mode. Each enabled interrupt can be used to wake up the chip from
Power-down mode.
7.10.1
Features
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
7.11 Ethernet (LPC1758 only)
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus
through the AHB-multilayer matrix to access the various on-chip SRAM blocks for
Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII
(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial
bus.
The Ethernet block supports bus clock rates of up to 100 MHz.
7.11.1
Features
Ethernet standards support:
–
Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
–
Fully compliant with
IEEE standard 802.3
.
–
Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
–
Flexible transmit and receive frame options.
–
Virtual Local Area Network (VLAN) frame support.
Memory management:
–
Independent transmit and receive buffers memory mapped to shared SRAM.
–
DMA managers with scatter/gather DMA and arrays of frame descriptors.
–
Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC2101FBD48 | Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC |
| LPC2102FBD48 | Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC |
| LPC2102FHN48 | Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC |
| LPC2103FBD48 | Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC |
| LPC2103FHN48 | Single-chip 16-bit-32-bit microcontrollers; 8 kB-16 kB-32 kB flash with ISP-IAP, fast ports and 10-bit ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC1751FBD80,551 | 功能描述:ARM微控制器 - MCU ARM Cortex M3 Micro Controller RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC1751FBD80551 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 100MHZ LQFP-80 |
| LPC1752 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN |
| LPC1752FBD80 | 制造商:NXP Semiconductors 功能描述:MCU 32BIT ARM CORTEX M3 80LQFP 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM CORTEX M3, 80LQFP 制造商:NXP Semiconductors 功能描述:IC, 32BIT MCU, ARM CORTEX, 100MHZ LQFP80; Controller Family/Series:(ARM Cortex); Core Size:32bit; No. of I/O's:52; Supply Voltage Min:2.4V; Supply Voltage Max:3.6V; Digital IC Case Style:LQFP; No. of Pins:80; Program Memory Size:64KB;RoHS Compliant: Yes |
| LPC1752FBD80,551 | 功能描述:ARM微控制器 - MCU ARM Cortex M3 Micro Controller RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。