參數(shù)資料
型號(hào): LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁(yè)數(shù): 34/74頁(yè)
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
34 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
7.30 System control
7.30.1
Reset
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see
description in
Section 7.29.4
). The wake-up timer ensures that reset remains asserted
until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks
have passed, and the flash controller has completed its initialization. Once reset is
de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD
threshold, the RSTOUT pin goes HIGH.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Fig 5.
Power distribution
REAL-TIME CLOCK
BACKUP REGISTERS
REGULATOR
32 kHz
OSCILLATOR
RTC POWER DOMAIN
MAIN POWER DOMAIN
002aad978
RTCX1
RTCX2
VBAT
V
DD(REG)(3V3)
V
DD(3V3)
V
SS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
ADC POWER DOMAIN
V
DDA
VREFP
VREFN
V
SSA
LPC17xx
ULTRA LOW-POWER
REGULATOR
POWER
SELECTOR
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