參數(shù)資料
型號: LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁數(shù): 56/74頁
文件大小: 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
56 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
11.9 SPI
Table 16.
T
amb
=
40
C to +85
C.
Symbol
T
cy(PCLK)
T
SPICYC
t
SPICLKH
t
SPICLKL
SPI master
t
SPIDSU
t
SPIDH
t
SPIQV
t
SPIOH
SPI slave
t
SPIDSU
t
SPIDH
t
SPIQV
t
SPIOH
[1]
T
SPICYC
= (T
cy(PCLK)
n)
0.5 %, n is the SPI clock divider value (n
8); PCLK is derived from the
processor clock CCLK.
[2]
Timing parameters are measured with respect to the 50 % edge of the clock PCLK and the 10 % (90 %)
edge of the data signal (MOSI or MISO).
Dynamic characteristics of SPI pins
Parameter
PCLK cycle time
SPI cycle time
SPICLK HIGH time
SPICLK LOW time
Min
10
79.6
0.485
T
SPICYC
Typ
-
-
-
-
Max
-
-
-
0.515
T
SPICYC
ns
Unit
ns
ns
ns
[1]
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
[2]
0
2
T
cy(PCLK)
5
2
T
cy(PCLK)
+ 30
2
T
cy(PCLK)
+ 5
-
-
-
-
-
-
-
-
ns
ns
ns
ns
[2]
[2]
[2]
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
[2]
0
2
T
cy(PCLK)
+ 5
2
T
cy(PCLK)
+ 35
2
T
cy(PCLK)
+ 15
-
-
-
-
-
-
-
-
ns
ns
ns
ns
[2]
[2]
[2]
Fig 21. SPI master timing (CPHA = 1)
SCK (CPOL = 0)
MOSI
MISO
002aad986
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPIQV
DATA VALID
DATA VALID
t
SPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID
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