參數(shù)資料
型號: LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁數(shù): 52/74頁
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
52 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
11.6 I
2
S-bus interface (LPC1759/58/56 only)
[1]
CCLK = 20 MHz; peripheral clock to the I
2
S-bus interface PCLK =
CCLK
4
; T
cy(clk)
= 1600 ns, corresponds to the SCK signal in the
I
2
S-bus specification
.
Table 13.
T
amb
=
40
C to +85
C.
Symbol
Parameter
common to input and output
t
r
rise time
t
f
fall time
t
WH
pulse width HIGH
Dynamic characteristics: I
2
S-bus interface pins
Conditions
Min
Typ
Max
Unit
[1]
-
-
0.495
T
cy(clk)
-
-
-
35
35
-
ns
ns
-
[1]
on pins I2STX_CLK and
I2SRX_CLK
on pins I2STX_CLK and
I2SRX_CLK
[1]
t
WL
pulse width LOW
[1]
-
-
0.505
T
cy(clk)
ns
output
t
v(Q)
data output valid time
on pin I2STX_SDA;
on pin I2STX_WS
[1]
-
-
-
-
30
30
ns
ns
[1]
input
t
su(D)
t
h(D)
data input set-up time
data input hold time
on pin I2SRX_SDA
on pin I2SRX_SDA
[1]
3.5
4.0
-
-
-
-
ns
ns
[1]
Fig 17. I
2
S-bus timing (output)
002aad992
I2STX_CLK
I2STX_SDA
I2STX_WS
T
cy(clk)
t
f
t
r
t
WH
t
WL
t
v(Q)
t
v(Q)
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