參數(shù)資料
型號(hào): LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁數(shù): 11/74頁
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
11 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
P2[8]/TD2/
TXD2
50
[1]
I/O
O
O
I/O
O
P2[8] —
General purpose digital input/output pin.
TD2 —
CAN2 transmitter output. (LPC1759/58/56 only).
TXD2 —
Transmitter output for UART2.
P2[9] —
General purpose digital input/output pin.
USB_CONNECT —
Signal used to switch an external 1.5 k
resistor under
software control. Used with the SoftConnect USB feature.
RXD2 —
Receiver input for UART2.
P2[10] —
General purpose digital input/output pin. A LOW level on this pin during
reset starts the ISP command handler.
EINT0 —
External interrupt 0 input.
NMI —
Non-maskable interrupt input.
Port 4:
Port 4 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 4 pins depends upon the pin function selected via the pin connect
block. Some port pins are not available on the LQFP80 package.
P4[28] —
General purpose digital input/output pin.
RX_MCLK —
I
2
S receive master clock. (LPC1759/58/56 only).
MAT2[0] —
Match output for Timer 2, channel 0.
TXD3 —
Transmitter output for UART3.
P4[29] —
General purpose digital input/output pin.
TX_MCLK —
I
2
S transmit master clock. (LPC1759/58/56 only).
MAT2[1] —
Match output for Timer 2, channel 1.
RXD3 —
Receiver input for UART3.
TDO —
Test Data out for JTAG interface.
SWO —
Serial wire trace output.
TDI —
Test Data in for JTAG interface.
TMS —
Test Mode Select for JTAG interface.
SWDIO —
Serial wire debug data input/output.
TRST —
Test Reset for JTAG interface.
TCK —
Test Clock for JTAG interface.
SWDCLK —
Serial wire clock.
RSTOUT —
This is a 3.3 V pin. LOW on this pin indicates
LPC1759/58/56/54/52/51 being in Reset state.
External reset input:
A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground:
0 V reference.
P2[9]/
USB_CONNECT/
RXD2
49
[1]
I
I/O
P2[10]/EINT0/NMI
41
[5]
I
I
I/O
P4[0] to P4[31]
P4[28]/RX_MCLK/
MAT2[0]/TXD3
65
[1]
I/O
I
O
O
I/O
I
O
I
O
O
I
I
I/O
I
I
I
O
P4[29]/TX_MCLK/
MAT2[1]/RXD3
68
[1]
TDO/SWO
1
[6]
TDI
TMS/SWDIO
2
[7]
3
[7]
TRST
TCK/SWDCLK
4
[7]
5
[6]
RSTOUT
11
RESET
14
[8]
I
XTAL1
XTAL2
RTCX1
RTCX2
V
SS
19
[9][10]
20
[9][10]
13
[9][11]
15
[9]
24, 33,
43, 57,
66, 78
I
O
I
O
I
Table 3.
Symbol
Pin description
…continued
Pin
Type
Description
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