
802.3u MII
2-31
interface pins MDC and MDIO for 10/100/1000 Mbit/s operation. The
L80600 implements all the required MII registers as well as several
optional registers. These registers are fully described in
Chapter 4,
“Registers.”
A description of the serial management access protocol
follows.
2.10.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management Data Clock
(MDC) and Management Data Input/Output (MDIO). MDC has a
maximum clock rate of 2.5 MHz and no minimum rate. The MDIO line is
bidirectional and may be shared by up to 32 devices. The MDIO frame
format is shown below in
Table 2.3
.
The MDIO pin requires a pull-up resistor (1.5 k
) which, during IDLE and
turnaround, pulls MDIO HIGH. To initialize the MDIO interface, the station
management entity sends a sequence of 32 contiguous logic ones on
MDIO to provide the L80600 with a sequence that can be used to
establish synchronization. This preamble may be generated either by
driving MDIO HIGH for 32 consecutive MDC clock cycles, or by simply
allowing the MDIO pull-up resistor to pull the MDIO pin HIGH during
which time 32 MDC clock cycles are provided. In addition, 32 MDC clock
cycles should be used to resynchronize the device if an invalid start,
opcode, or turnaround bit is detected.
The L80600 waits until it has received this preamble sequence before
responding to any other transaction. Once the L80600 serial
management port has been initialized, no further preamble sequencing
is required until after a power-on/reset, invalid start, invalid opcode, or
invalid turnaround bit has occurred.
The Start code is indicated by an <01> pattern. This assures the MDIO
line transitions from the default idle line state.
Table 2.3
Typical MDIO Frame Format
MII Management
Serial Protocol
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>