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參數(shù)資料
| 型號(hào)： | L80600 |
| 英文描述： | L80600 10/100/1000 Mbits/s Ethernet PHY technical manual 3/01 |
| 中文描述： | L80600 10/100/1000 Mbits /秒以太網(wǎng)PHY技術(shù)手冊(cè)3月1日 |
| 文件頁(yè)數(shù)： | 129/192頁(yè) |
| 文件大?。?/td> | 1344K |
| 代理商： | L80600 |
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System Design Implementation Consideration
6-15
6.9.1 10 Mbits/s VOD
IEEE 802.3 specification, Clause 14, requires that the 10 Mbits/s output
levels be within the following limits:
VOD = 2.2 to 2.8 V peak-differential, when terminated by a 100
resistor
directly at the RJ-45 outputs. The L80600 10 Mbit/s output level is
typically 1.58 V peak-differential.
IEEE 802.3 specification, Clause 14, requires that a 10 Mbit/s PHY
should be able to correctly receive signal levels on Vin = 585 mV
peak-differential. It also requires that any signal that is less than 300 mV
peak-differential should be rejected by the PHY. The L80600 VOD level
of 1.58 V peak-differential is received at the link partner with magnitudes
exceeding Vin = 585 mV peak-differential for cables up to 150 meters of
CAT3 or CAT5 cables.
In 10 Mbit/s mode, the L80600 can receive and transmit up to
187 meters using CAT5 cable and up to 150 meters using CAT3 cable.
There is no system level impact on the receive ability of the link partner
due to the reduced levels of VOD transmitted by the L80600.
There are no plans to change the 10 Mbit/s VOD levels.
6.9.2 Asymmetrical Pause
IEEE 802.3ab has assigned bit 11 in register 0x04 to indicate
Asymmetrical Pause capability. In the L80600 this bit is a read only bit
with a default value of zero.
Asymmetrical Pause capability can be advertised by writing the PHY
software registers as follows through the MDIO interface:
Write to register 0x16 the value 0x0D
Write to register 0x1E the value 0x8084
Write to register 0x1D the value 0x0001
The order of the writes is important. Register 0x1E is a pointer to the
internal expanded addresses. Register 0x1D contains the data to be
written to or read from the internal address pointed by register 0x1E.The
contents of register 0x1E automatically increments after each read or
write to register 0x1D. Therefore, if one wants to confirm that the data
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