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參數(shù)資料
| 型號(hào)： | L64777 |
| 英文描述： | L64777 DVB QAM Modulator technical manual 6/00 |
| 中文描述： | L64777的DVB QAM調(diào)制器技術(shù)手冊(cè)6 / 00 |
| 文件頁(yè)數(shù)： | 105/124頁(yè) |
| 文件大小： | 988K |
| 代理商： | L64777 |
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Serial Bus Protocol Overview
A-3
Figure A.2
Serial Bus Write/Read Cycle
Start
Condition
Stop
Condition
SCL
SDA
R/W
Master-Transmitter, Slave-Receiver
(Master transmits slave address)
ACK Cycle: Slave
Master-Transmitter, Slave-Receiver
(Master transmits data to slave)
Write Cycle
bit7
bit6
bit5
bit3
bit2
bit1
bit0
bit4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
ACK Cycle: Slave
SDA
R/W
Master-Transmitter, Slave-Receiver
(Master transmits slave address)
ACK Cycle: Slave
Master-Receiver, Slave-Transmitter
(Slave transmits data to master)
Read Cycle (burst)
bit7
bit6
bit5
bit3
bit2
bit1
bit0
bit4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
ACK Cycle: Master
SDA
R/W
Master-Transmitter, Slave-Receiver
(Master transmits slave address)
ACK Cycle: Slave
Master-Receiver, Slave-Transmitter
(Slave transmits data to master)
Single-Read Cycle
bit7
bit6
bit5
bit3
bit2
bit1
bit0
bit4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
ACK Cycle: Master
Stop
Condition
bit7
Start Condition: The master (which drives the SCL) indicates the start of a cycle by pulling SDA to LOW when
SCL is HIGH.
Stop Condition: The master (which drives the SCL) indicates the end of a cycle by releasing SDA to HIGH when
SCL is HIGH.
Data Transfer: All data changes on the SDA line happen only when clock is LOW, except for the special cases
outlined above to indicate cycle Start/Stop.
Acknowledge: The receiver always generates the acknowledge. In the case of a single read, the master-receiver
does not generate an ACK so that it can generate the Stop condition (as indicated above).
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