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| 型號： | KM4216C258 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM) |
| 中文描述： | 256K × 16位的CMOS視頻RAM（256K × 16位的CMOS視頻內(nèi)存） |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 772K |
| 代理商： | KM4216C258 |
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KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
DEVICE OPERATIONS
( Continued)
If SRT1 and SRT2 are performed in succession before access-
ing the boundary like Fig. 9, the data transferred by SRT2
overwrites the data transferred by SRT1, so that data followed
by SRT2 will be remain in the upper half SAM. The Serial Read
after lower boundary 255th SC is started from the starting
address given by SRT2 cycle. The Fig. 10 indicates that SRT
cycle is not performed until Serial Read is completed to the
boundary location 511.
In this case, the internal serial counter is designed to designate
"0" address after boundary 511, therefore accessed data from 0
address corresponds to the old data transferred by RT. Note
that there is not allowed period of SRT cycle. Since a SRT cycle
must be ended before
t
STH
and started after
t
STS
, a split transfer
is not allowed during
t
STH
+
t
STS
(see Fig. 11)
A Split Read Transfer does not change the direction of the SAM
I/O port.
Figure 7. Split Read Transfer Normal Usage
RAS
CASL
CASU
A
0
~ A
8
QSF
SC
X1
X2
X2
0
Y
1
(A
8
= Don
′
t Care)
Y
1
511
256+Y
0
255
0
RT
SRT
SRT
X1 X2 X3 X4
A
A
′
B
′
C
′
D
′
B
C D
A
A
′
255
256
RAM
SAM
511
X1 Row Data Full Transfer
X1 X2 X3 X4
A
A
′
B
′
C
′
D
′
B
C
D
A
B
′
255
256
RAM
SAM
511
Upper SAM :
Half Transfer (X2 Row Data)
Lower SAM :
Serial Read (X1 Row Data)
0
X1 X2 X3 X4
A
A
′
B
′
C
′
D
′
B
C D
B
B
′
255
256
RAM
SAM
511
Upper SAM :
Serial Read (X2 Row Data)
0
Half Transfer (X2 Row Data)
Lower SAM :
0
Y
0
(A
8
= Don
′
t Care)
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