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參數(shù)資料
| 型號(hào)： | KM4216C258 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM) |
| 中文描述： | 256K × 16位的CMOS視頻RAM（256K × 16位的CMOS視頻內(nèi)存） |
| 文件頁數(shù)： | 11/41頁 |
| 文件大?。?/td> | 772K |
| 代理商： | KM4216C258 |
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KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
DEVICE OPERATIONS
The KM4216C258 contains 4,194,304 memory locations.
Eighteen address bits are required to address a particular 16 bit
word in the memory array. Since the KM4216C258 has only
9 address input pins, time multiplexed addressing is used to
input 9 row and 9 column addresses. The multiplexing is con-
trolled by the timing relationship between the row address strobe
(RAS), the column address strobe (CAS) and the valid row and
column address inputs.
Operation of the KM4216C258 begins by strobing in a valid row
address with RAS while CAS remains high. Then the address
on the 9 address input pins are changed from a row address to a
column address, and are strobed by CAS.
This is the beginning of any KM4216C/V256 cycle in which a
memory location is accessed. The specific type of cycle is deter-
mined by the state of the write enable pin and various timing
relationship. The cycle is terminated when both RAS and CAS
have returned to the high state. Another cycle can be initiated
after RAS remains high long enough to satisfy the RAS pre-
charge time(
t
RP
) requirement.
RAS and CAS Timing
The minimum RAS and CAS pulse widths are specified by
t
RAS
(min) and
t
CAS
(min) respectively. These minimum pulse
widths must be satisfied for proper device operation and data
integrity. Once a cycle is initiated by bringing RAS low, it must
not be aborted prior to satisfying the minimum RAS and CAS
pulse widths. In addition, a new cycle must not begin until the
minimum RAS precharge time,
t
RP
, has been satisfied. Once a
cycle begins, internal clocks and other circuits within the
KM4216C258 begin a complex sequence of events. If the
sequence is broken by violating minimum timing requirement,
loss of data integrity can occur.
RAM Read
A RAM read cycle is achieved by maintaining WB/WE high dur-
ing a RAS / CAS cycle. The access time is normally specified
with respect to the falling edge of RAS. But the access time also
depends on the falling edge of CAS and on the valid column
address transition.
If CAS goes low before
t
RCD
(max) and if the column address is
valid before
t
RAD
(max) then the access time to valid data is
specified by
t
RAC
. However, If CAS goes low after
t
RCD
(max) or
the column address becomes valid after
t
RAD
(max), access is
specified by
t
CAC
or
t
AA
.
The KM4216C258 has common data I/O pins. The DT/OE has
been provided so the output buffer can be precisely controlled.
For data to appear at the outputs, DT/OE must be low for the
period of time defined by
t
OEA
.
Extended Data Out
In the conventional RAM Read cycle, Dout buffer is designed to
make turn-off by the rising edge of CAS. the KM4216C258 offers
an accelerated Fast Page Mode cycle by eliminating output dis-
able from CAS high. This is called "Extended Data Output (or
Hyper Page) mode". Data outputs are disabled at WB/WE =
Low, DT/OE = High and
t
OFF
time after RAS and CAS are high
The
t
OFF
time is referenced from rising edge of RAS or CAS,
whichever occurs later (see Figure 1). What the output buffer is
disabling during DT/OE = high is to use bank selection in the
frame buffer memory using common I/O line, Read, Write and
Read-modify-write cycles are available during the extended data
out mode.
RAS
Read
Read
(OE)
Read
Write
Read
t
OEHC
t
OCH
Row
Col.(B)
Col.(C)
t
RAC
t
t
CAC
t
AA
t
CPA
t
DOH
t
OEZ
t
OFF(CAS)
t
OFF(RAS)
t
OEA
t
AA
Hi - Z
t
DH
t
DS
Col.(D)
Col.(E)
t
OEZ
t
WEZ
A
B
C
D
E
CASL,CASU
DT/OE
WB/WE
W
0
/DQ
0
~
W
15
/DQ
15
A
0
~ A
8
Col.(A)
Data Out
Data Out
Data In
Hi - Z
t
CAC
Figure 1. Extended Data Output Example
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM4216V256 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256K X 16 BIT CMOS VIDEO RAM |
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