參數(shù)資料
型號: KM4216C258
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM)
中文描述: 256K × 16位的CMOS視頻RAM(256K × 16位的CMOS視頻內(nèi)存)
文件頁數(shù): 13/41頁
文件大?。?/td> 772K
代理商: KM4216C258
KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
EARLY or LATE WRITE
RAS
CASL
WB/WE
W
0
/DQ
0~
W
7
/DQ
7
W
15
/DQ
15
Lower Byte No Write
Upper Byte Masked Early Write
Valid Data-in CASU Falling
Mask Data
Valid Data-in
Valid Data-in
t
MS
t
MH
t
DS
t
DH
t
DS
t
DH
W
8
/DQ
8~
If Early Write
Lower Byte No Write
Upper Byte Masked Late Write
Valid Data-in WB/WE Falling
If Late Write
Lower Byte No Write
Upper Byte Early Write
Valid Data-in CASL Falling
If Early Write
Lower Byte No Write
Upper Byte Late Write
Valid Data-in WB/WE Falling
If Late Write
Fast Page Mode
The KM4216C258 has Fast Page Mode capability provides high
speed read, write or read-modify-write access to all memory
locations within a selected row. In this cycle, read, write, read-
modify-write, and block write cycles can be mixed in any order.
In one RAS cycle, 512 word memory cells of the same row
address can be accessed. While RAS is held low to maintain the
row address, CAS is cycled to strobe in additional column
addresses. This eliminates the time required to set up and
strobe sequential row addresses for the same page.
Load Color Register (LCR)
A Load Color Register cycle is performed by keeping DSF high
on the both the falling edges of RAS and CAS. Color data is
loaded on the falling edge of CAS (early write) or WE (late write)
via the W
0
/DQ
0
~ W
7
/DQ
7
(lower byte), W
8
/DQ
8
~ W
15
/DQ
15
(upper byte) pins. This data is used in Block Write cycles and
remains unchanged until the next Load Color Register cycle.
CASU
Valid Data-in
Mask Data
DEVICE OPERATIONS
( Continued)
Figure 3. Byte Write and New Masked Write Cycle Example2.
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